Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git...

Merge tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull irq chip driver updates from Thomas Gleixner:

 - Add support for the Renesas RZ/V2N SoC

 - Add a new driver for the Renesas RZ/[TN]2H SoCs

 - Preserve the register state of the RISCV APLIC interrupt controller
   accross suspend/resume

 - Reinitialize the RISCV IMSIC registers after suspend/resume

 - Make the various Loongson interrupt chip drivers 32/64-bit aware

 - Handle the number of hardware interrupts in the SIFIVE PLIC driver
   correctly

   The hardware interrupt 0 is reserved which resulted in inconsistent
   accounting. That went unnoticed as the off by one is only noticable
   when the number of device interrupts is a multiple of 32

 - The usual device tree updates, cleanups and improvements all over the
   place

* tag 'irq-drivers-2026-02-09' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (24 commits)
  irqchip/gic-v5: Fix spelling mistake "ouside" -> "outside"
  dt-bindings: interrupt-controller: sifive,plic: Clarify the riscv,ndev meaning in PLIC
  irqchip/sifive-plic: Handle number of hardware interrupts correctly
  irqchip/aspeed-scu-ic: Remove unused variable mask
  irqchip/ti-sci-intr: Allow parsing interrupt-types per-line
  dt-bindings: interrupt-controller: ti,sci-intr: Per-line interrupt-types
  irqchip/renesas-rzv2h: Add suspend/resume support
  irqchip/aslint-sswi: Fix error check of of_io_request_and_map() result
  irqchip: Allow LoongArch irqchip drivers on both 32BIT/64BIT
  irqchip/loongson-pch-pic: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-pch-msi: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-htvec: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-eiointc: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongson-liointc: Adjust irqchip driver for 32BIT/64BIT
  irqchip/loongarch-avec: Adjust irqchip driver for 32BIT/64BIT
  irqchip/riscv-aplic: Preserve APLIC states across suspend/resume
  irqchip/riscv-imsic: Add a CPU pm notifier to restore the IMSIC on exit
  arm64: dts: renesas: r9a09g087: Add ICU support
  arm64: dts: renesas: r9a09g077: Add ICU support
  irqchip: Add RZ/{T2H,N2H} Interrupt Controller (ICU) driver
  ...