RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init

When broadcast the reperated element, we take the mask_int_mode
by mistake. This patch would like to fix it by leveraging the machine
mode of the element.

The below test case in RV32 will be fixed.

* gcc/testsuite/gfortran.dg/overload_5.f90

	PR target/111546

gcc/ChangeLog:

	* config/riscv/riscv-v.cc
	(expand_vector_init_merge_repeating_sequence): Bugfix

Signed-off-by: Pan Li <pan2.li@intel.com>