RISC-V: Fix incorrect optimization options passing to cond and builtin

RISC-V: Fix incorrect optimization options passing to cond and builtin

Like the strided load/store, the testcases of vector cond and builtin are
designed to pick up different sorts of optimization options but actually
these option are ignored according to the Execution log of gcc.log.
This patch would like to make it correct almost the same as what we
fixed for strided load/store.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/rvv.exp: Fix the incorrect optimization
	options passing to testcases.

Signed-off-by: Pan Li <pan2.li@intel.com>