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(parent: af98cae) | patch
clk: at91: clk-master: Add check for divide by 3
authorRyan Wanner <Ryan.Wanner@microchip.com>
Mon, 8 Sep 2025 20:07:17 +0000 (13:07 -0700)
committerNicolas Ferre <nicolas.ferre@microchip.com>
Wed, 17 Sep 2025 17:15:32 +0000 (19:15 +0200)
commite0237f5635727d64635ec6665e1de9f4cacce35c
tree463a35def2787c6d86052c60a5147b9f65c34118tree | snapshot
parentaf98caeaa7b6ad11eb7b7c8bfaddc769df2889f3commit | diff
clk: at91: clk-master: Add check for divide by 3

A potential divider for the master clock is div/3. The register
configuration for div/3 is MASTER_PRES_MAX. The current bit shifting
method does not work for this case. Checking for MASTER_PRES_MAX will
ensure the correct decimal value is stored in the system.

Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
drivers/clk/at91/clk-master.c diff | blob | blame | history
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