[to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

[to-be-committed][RISC-V][PR target/115142] Do not create invalidate shift-add insn

The circumstances which triggered this weren't something that should appear in
the wild (-ftree-ter, without optimization enabled).  So I wasn't planning to
backport.  Obviously if it shows up in another context we can revisit that
decision.

I've run this through my rv32gcv and rv64gc tester.  Waiting on the CI system before committing.

	PR target/115142
gcc/

	* config/riscv/riscv.cc (mem_shadd_or_shadd_rtx_p): Make sure
	shifted argument is a register.

gcc/testsuite

	* gcc.target/riscv/pr115142.c: New test.