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clk: imx: fracn-gppll: Add 333.333333 MHz support
authorAlexander Stein <alexander.stein@ew.tq-group.com>
Fri, 13 Mar 2026 07:07:31 +0000 (08:07 +0100)
committerAbel Vesa <abel.vesa@oss.qualcomm.com>
Thu, 19 Mar 2026 14:12:13 +0000 (16:12 +0200)
commite2f8311a6aa5f809bb62de61888292e58087fd21
treed0b4c3c61b4f47b8b5a248f0fcee2faa6f9cf1e1tree | snapshot
parentfca8688a6798f6fee6b86ce0bc39d1cd0b1c8b8acommit | diff
clk: imx: fracn-gppll: Add 333.333333 MHz support

Some parallel panels have a pixelclk of 33.30 MHz. Add support for
333.333333 MHz so a by 10 divider can be used to derive the exact pixelclk.

Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20260313070740.585043-2-alexander.stein@ew.tq-group.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
drivers/clk/imx/clk-fracn-gppll.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git