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(parent: 0312e94) | patch
riscv: fix test_and_{set,clear}_bit ordering documentation
authorIgnacio Encinas <ignacio@iencinas.com>
Tue, 11 Mar 2025 17:20:22 +0000 (18:20 +0100)
committerYury Norov <yury.norov@gmail.com>
Wed, 12 Mar 2025 23:27:15 +0000 (19:27 -0400)
commite3f42c436d7e0cb432935fe3ae275dd8d9b60f71
tree08c4b9178b68a417bfe447979b4649a5e5e30a17tree
parent0312e94abe484b9ee58c32d2f8ba177e04955b35commit | diff
riscv: fix test_and_{set,clear}_bit ordering documentation

test_and_{set,clear}_bit are fully ordered as specified in
Documentation/atomic_bitops.txt. Fix incorrect comment stating otherwise.

Note that the implementation is correct since commit
9347ce54cd69 ("RISC-V: __test_and_op_bit_ord should be strongly ordered")
was introduced.

Signed-off-by: Ignacio Encinas <ignacio@iencinas.com>
Signed-off-by: Yury Norov <yury.norov@gmail.com>
arch/riscv/include/asm/bitops.h diff | blob | blame | history
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