aarch64: GICv5 CPU interface system registers

aarch64: GICv5 CPU interface system registers

This patch adds support for 13 new AArch64 system registers for the CPU
interface, which are enabled on using Generic Interrupt Controller v5
(+gcie flag) feature:
- 7 R/W registers: ICC_APR_EL1, ICC_APR_EL3, ICC_CR0_EL1, ICC_CR0_EL3
  ICC_ICSR_EL1, ICC_PCR_EL1, ICC_PCR_EL3.
- 6 RO registers: ICC_DOMHPPIR_EL3, ICC_HAPR_EL1, ICC_HPPIR_EL1,
  ICC_HPPIR_EL3, ICC_IAFFIDR_EL1, ICC_IDR0_EL1.

Note: the already-existing ID_AA64PFR2_EL1 register is required by the
GICv5 feature.