mtd: spi-nor: Add gd55lb02gf chips

mtd: spi-nor: Add gd55lb02gf chips

Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with
the same read path flags.

SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's
status register layout: the GD55LB02GF uses a 5-bit block protect
field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet
"Status Register Block Protection").

The generic stm-lock helpers drive only BP0..BP2 and assume SR1
bit 5 is TB, but on this part SR1 bit 5 is BP3.
Enabling either flag would leave BP3..BP4 unmanaged or corrupt
BP3 on every lock op.
A proper support needs a vendor specific lock callback, it is out
of scope for this table update.

Signed-off-by: Vincent Jardin <vjardin@free.fr>
Suggested-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Takahiro Kuwano <takahiro.kuwano@infineon.com>