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(parent: 8fe7514) | patch
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE
authorzhongjuzhe <juzhe.zhong@rivai.ai>
Tue, 30 Aug 2022 06:27:52 +0000 (14:27 +0800)
committerKito Cheng <kito.cheng@sifive.com>
Thu, 1 Sep 2022 02:01:54 +0000 (10:01 +0800)
commite8c83ab9d5142a305bbd75c7ff0e41eae38433df
tree691a0eb211372248a618fe4f27577003c58b80fdtree
parent8fe75147a948ceab6fb9afbe0ee698517ce1dda0commit | diff
RISC-V: Add vector registers in TARGET_CONDITIONAL_REGISTER_USAGE

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_conditional_register_usage): Add vector
registers.
gcc/config/riscv/riscv.cc diff | blob | blame | history
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