]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
dt-bindings: riscv: add vector sub-extension dependencies
authorConor Dooley <conor.dooley@microchip.com>
Wed, 12 Mar 2025 13:11:48 +0000 (13:11 +0000)
committerAlexandre Ghiti <alexghiti@rivosinc.com>
Tue, 25 Mar 2025 14:19:35 +0000 (14:19 +0000)
commite9f1d61a5e186092d3b8eaa411bb4a76622bf854
tree9332997c37a1a64bb8d541a06de00a320edfa71f
parent534d813a06202c565b4a7e75a3e710db7155e6d3
dt-bindings: riscv: add vector sub-extension dependencies

Section 33.18.2. Zve*: Vector Extensions for Embedded Processors
in [1] says:
| The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve64f extension depends
| on the Zve32f and Zve64x extensions. The Zve64d extension depends on the Zve64f extension

| The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64f extensions depend
| upon the F extension

| The Zve64d extension depends upon the D extension

Apply these rules to the bindings to help prevent invalid combinations.

Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-release-698e64a-2024-09-09
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250312-banking-crestless-58f3259a5018@spud
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Documentation/devicetree/bindings/riscv/extensions.yaml