RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

RISC-V: Fix bugs of handling scalar of SEW64 vx instruction in RV32

sew64_scalar_helper is handling SEW64 vx instruction pattern on RV32 system.
According to RVV ISA, we can directly use vx instruction of SEW64 on RV32 system
since RV32 GR reg is 32bit.

Consider this following case:

vsetvl e64m1
vadd.vx v,v,x

will be transform by sew64_scalar_helper:

vsetvl e64m1
sw
sw
vlse v
vadd.vv

This bug is reported by Robin.
(insn 143 179 230 9 (set (reg:SI 15 a5 [234])
        (unspec:SI [
                (const_int 64 [0x40])
            ] UNSPEC_VLMAX)) 751 {vlmax_avlsi}
     (expr_list:REG_EQUIV (unspec:SI [
                (const_int 64 [0x40])
            ] UNSPEC_VLMAX)
        (nil)))
(insn 230 143 78 9 (parallel [
            (set (reg:SI 66 vl)
                (unspec:SI [
                        (reg:SI 15 a5 [234])
                        (const_int 64 [0x40])
                        (const_int 0 [0])
                    ] UNSPEC_VSETVL))
            (set (reg:SI 67 vtype)
                (unspec:SI [
                        (const_int 64 [0x40])
                        (const_int 0 [0])
                        (const_int 1 [0x1]) repeated x2
                    ] UNSPEC_VSETVL))
        ]) "bug.c":14:14 discrim 1 1469 {vsetvl_discard_resultsi}
     (nil))
(insn 78 230 84 9 (set (reg:RVVM1DI 102 v6 [203])
        (if_then_else:RVVM1DI (unspec:RVVMF64BI [
                    (const_vector:RVVMF64BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (const_int 0 [0])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                ] UNSPEC_VPREDICATE)
            (vec_duplicate:RVVM1DI (mem/u/c:DI (reg/f:SI 29 t4 [230]) [0  S8 A64]))
            (unspec:RVVM1DI [
                    (reg:SI 0 zero)
                ] UNSPEC_VUNDEF))) "bug.c":14:14 discrim 1 1872 {*pred_broadcastrvvm1di}
     (expr_list:REG_DEAD (reg/f:SI 29 t4 [230])
        (nil)))

The root cause of this is because we missed VLMAX handling since the codes was invented
long time ago (Callers always intrinsics codes, no VLMAX situation).

Now, all following bugs are fixed after this patch:

FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test
FAIL: gcc.target/riscv/rvv/autovec/unop/popcount-run-1.c execution test

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (sew64_scalar_helper): Fix bug.
	* config/riscv/riscv-v.cc (sew64_scalar_helper): Ditto.
	* config/riscv/vector.md: Ditto.