]> git.ipfire.org Git - thirdparty/kernel/stable.git/commit
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588
authorCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Tue, 4 Feb 2025 12:40:08 +0000 (14:40 +0200)
committerHeiko Stuebner <heiko@sntech.de>
Thu, 6 Feb 2025 11:01:34 +0000 (12:01 +0100)
commiteb4262203d7d85eb7b6f2696816db272e41f5464
treedc4dd81dbd65d04bbe71e3a4bd2e99f4b196bac4
parentd0f17738778c12be629ba77ff00c43c3e9eb8428
arm64: dts: rockchip: Add HDMI0 PHY PLL clock source to VOP2 on RK3588

VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and
more accurate pixel clock source to improve handling of display modes up
to 4K@60Hz on video ports 0, 1 and 2.

For now only HDMI0 output is supported, hence add the related PLL clock.

Tested-by: FUKAUMI Naoki <naoki@radxa.com>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20250204-vop2-hdmi0-disp-modes-v3-5-d71c6a196e58@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi