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clk: renesas: r9a09g056: Add clock and reset entries for TSU
authorOvidiu Panait <ovidiu.panait.rb@renesas.com>
Tue, 9 Dec 2025 09:11:14 +0000 (09:11 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 29 Dec 2025 10:43:22 +0000 (11:43 +0100)
commitebb3acf4d7c95b52265084168b59a565bf972883
tree41c1257cfe9a02b18eb55ec0a96f3f3142be8c6ctree
parent2efea3b35cc916f04f06b89f2e2557dbd9c48109commit | diff
clk: renesas: r9a09g056: Add clock and reset entries for TSU

Add module clock and reset entries for the TSU0 and TSU1 blocks on the
Renesas RZ/V2N (R9A09G056) SoC.

Signed-off-by: Ovidiu Panait <ovidiu.panait.rb@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251209091115.8541-3-ovidiu.panait.rb@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a09g056-cpg.c diff | blob | blame | history
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