]> git.ipfire.org Git - thirdparty/linux.git/commit
phy: qcom-qmp: pcs-pcie: Add v8 register offsets
authorQiang Yu <qiang.yu@oss.qualcomm.com>
Mon, 24 Nov 2025 10:24:36 +0000 (02:24 -0800)
committerVinod Koul <vkoul@kernel.org>
Tue, 23 Dec 2025 17:41:04 +0000 (23:11 +0530)
commitecc12453c8b1aabdedcd663b7e0587f372a2a90d
tree6f8e2e423b00a9edd68aa87f740b9d1d0061a4b9
parent5359da47e066edb3fcd36c7349726913ee8628f2
phy: qcom-qmp: pcs-pcie: Add v8 register offsets

Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new
PCS PCIE specific offsets in a dedicated header file.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-3-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v8.h [new file with mode: 0644]