In testing issues with the new ISA 3.0 instructions in BE mode, it was
found that we needed some more unique values in the operands to catch
various errors. The issue is a sigle 32-bit value was replicated four
times for a V128 operand. The result is testing loads and stores where
the word or half word order was swizzled couln't be detected because
they were the same. By making the 32-bit chunks unique we were able
to catch additional errors.
The VEX instruction fixes was committed in VEX commit 3260.