RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

RISC-V: Support -mcpu for XiangShan Kunminghu cpu.

This patch adds support for the XiangShan Kunminghu CPU in GCC, allowing
the use of the `-mcpu=xiangshan-kunminghu` option.

XiangShan-KunMingHu is the third-generation open-source high-performance
RISC-V processor.[1] You can find the corresponding ISA extension from the
XiangShan Github repository.[2] The latest news of KunMingHu can be found
in the XiangShan Biweekly.[3]

[1] https://github.com/OpenXiangShan/XiangShan-User-Guide/releases.
[2] https://github.com/OpenXiangShan/XiangShan/blob/master/src/main/scala/xiangshan/Parameters.scala
[3] https://docs.xiangshan.cc/zh-cn/latest/blog

A dedicated scheduling model for KunMingHu's hybrid pipeline will be
proposed in a subsequent PR.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): New cpu tune.
	(RISCV_CORE): New cpu.
	* doc/invoke.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/mcpu-xiangshan-kunminghu.c: New test.

Co-Authored-By: Jiawei Chen <jiawei@iscas.ac.cn>
Co-Authored-By: Yangyu Chen <cyy@cyyself.name>
Co-Authored-By: Tang Haojin <tanghaojin@outlook.com>