Rework constant subreg folds and handle more variable-length cases

Rework constant subreg folds and handle more variable-length cases

This patch rewrites the way simplify_subreg handles constants.
It uses similar native_encode/native_decode routines to the
tree-level handling of VIEW_CONVERT_EXPR, meaning that we can
move between rtx constants and the target memory image of them.

The main point of this patch is to support subregs of constant-length
vectors for VLA vectors, beyond the very simple cases that were already
handled.  Many of the new tests failed before the patch for variable-
length vectors.

The boolean side is tested more by the upcoming SVE ACLE work.

2019-09-19  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* defaults.h (TARGET_UNIT): New macro.
	(target_unit): New type.
	* rtl.h (native_encode_rtx, native_decode_rtx)
	(native_decode_vector_rtx, subreg_size_lsb): Declare.
	(subreg_lsb_1): Turn into an inline wrapper around subreg_size_lsb.
	* rtlanal.c (subreg_lsb_1): Delete.
	(subreg_size_lsb): New function.
	* simplify-rtx.c: Include rtx-vector-builder.h
	(simplify_immed_subreg): Delete.
	(native_encode_rtx, native_decode_vector_rtx, native_decode_rtx)
	(simplify_const_vector_byte_offset, simplify_const_vector_subreg): New
	functions.
	(simplify_subreg): Use them.
	(test_vector_subregs_modes, test_vector_subregs_repeating)
	(test_vector_subregs_fore_back, test_vector_subregs_stepped)
	(test_vector_subregs): New functions.
	(test_vector_ops): Call test_vector_subregs for integer vector
	modes with at least 2 elements.

From-SVN: r275959