]> git.ipfire.org Git - thirdparty/linux.git/commit
drm/xe/xe_survivability: Redesign survivability mode
authorRiana Tauro <riana.tauro@intel.com>
Mon, 8 Dec 2025 08:45:41 +0000 (14:15 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 9 Dec 2025 22:19:42 +0000 (17:19 -0500)
commitf4e9fc967afdb53b1203f894fb4b68451a7fe202
treebbd95bf865ac9112204292d31e5f8e1581692b9e
parenta00e305fba02a915cf2745bf6ef3f55537e65d57
drm/xe/xe_survivability: Redesign survivability mode

Redesign survivability mode to have only one value per file.

1) Retain the survivability_mode sysfs to indicate the type

cat /sys/bus/pci/devices/0000\:03\:00.0/survivability_mode
(Boot / Runtime)

2) Add survivability_info directory to expose boot breadcrumbs.
Entries in survivability mode sysfs are only visible when
boot breadcrumb registers are populated.

/sys/bus/pci/devices/0000:03:00.0/survivability_info
├── aux_info0
├── aux_info1
├── aux_info2
├── aux_info3
├── aux_info4
├── capability_info
├── postcode_trace
└── postcode_trace_overflow

Capability Info:

Provides data about boot status and has bits that
indicate the support for the other breadcrumbs

Postcode Trace / Postcode Trace Overflow :

Each postcode is represented as an 8-bit value and represents
a boot failure event. When a new failure event is logged by Pcode
the existing postcodes are shifted left. These entries provide a
history of 8 postcodes.

Auxiliary Info:

Some failures have additional debug information.

Signed-off-by: Riana Tauro <riana.tauro@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patch.msgid.link/20251208084539.3652902-5-riana.tauro@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_survivability_mode.c
drivers/gpu/drm/xe/xe_survivability_mode_types.h