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clk: tegra20: Reparent dsi clock to pll_d_out0
authorSvyatoslav Ryhel <clamor95@gmail.com>
Thu, 4 Dec 2025 06:17:00 +0000 (08:17 +0200)
committerThierry Reding <treding@nvidia.com>
Sat, 17 Jan 2026 00:17:42 +0000 (01:17 +0100)
commitf521678d1921e0c1a206fa03a87b318d3e97d89b
treec115973427c3998a46f12aca4365f93808f211e3tree
parent2ea99dade57e094625726de1ced1e99b48fc767acommit | diff
clk: tegra20: Reparent dsi clock to pll_d_out0

Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra20.c diff | blob | blame | history
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