RISC-V: Add Shlcofideleg extension.

RISC-V: Add Shlcofideleg extension.

This patch add the RISC-V Shlcofideleg extension. It supports delegating
LCOFI interrupts(the count-overflow interrupts) to VS-mode.[1]

[1] https://riscv.github.io/riscv-isa-manual/snapshot/privileged

gcc/ChangeLog:

	* config/riscv/riscv-ext.def: New extension defs.
	* config/riscv/riscv-ext.opt: Ditto.
	* doc/riscv-ext.texi: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/arch-shlocofideleg.c: New test.

Signed-off-by: Jiawei <jiawei@iscas.ac.cn>