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(parent: 819bf66) | patch
drm/amd/display: Correct register address in dcn35
authorloanchen <lo-an.chen@amd.com>
Wed, 15 Jan 2025 09:43:29 +0000 (17:43 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 28 Jan 2025 21:23:30 +0000 (16:23 -0500)
commitf88192d2335b5a911fcfa09338cc00624571ec5e
tree37b70d4634bf02dcb144c72265acf9a462e1c5b2tree | snapshot
parent819bf6662b93a5a8b0c396d2c7e7fab6264c9808commit | diff
drm/amd/display: Correct register address in dcn35

[Why]
the offset address of mmCLK5_spll_field_8 was incorrect for dcn35
which causes SSC not to be enabled.

Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Signed-off-by: Lo-An Chen <lo-an.chen@amd.com>
Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c diff | blob | blame | history
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