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(parent: c0df96b) | patch
RISC-V: Fix ternary instruction attribute bug
authorJuzhe-Zhong <juzhe.zhong@rivai.ai>
Mon, 29 May 2023 04:21:48 +0000 (12:21 +0800)
committerPan Li <pan2.li@intel.com>
Mon, 29 May 2023 04:21:48 +0000 (12:21 +0800)
commitf8af48d8755018272cdb0cf2f250cf278829d7be
tree0e30da50b0a2b43fd6f8af98d60cea51fb407606tree
parentc0df96b3cda5738afbba3a65bb054183c5cd5530commit | diff
RISC-V: Fix ternary instruction attribute bug

Fix bug of vector.md which generate incorrect information to
VSETVL PASS when testing FMA auto vectorization ternop-3.c.

Signed-off-by: Juzhe-Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:

* config/riscv/vector.md: Fix vimuladd instruction bug.
gcc/config/riscv/vector.md diff | blob | blame | history
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