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MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT
authorThomas Bogendoerfer <tsbogend@alpha.franken.de>
Mon, 14 Sep 2020 16:05:00 +0000 (18:05 +0200)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 23 Sep 2020 10:59:55 +0000 (12:59 +0200)
commitf8d4ba31972b8eff79a44b33a463bf07c73504fc
treeb0627af08841e0f79522303d2725ce2a0d5d86f8tree
parent5c44b2d15e2fd60e084b9035ddf4e127ffcfc6c8commit | diff
MIPS: SNI: Fix MIPS_L1_CACHE_SHIFT

[ Upstream commit 564c836fd945a94b5dd46597d6b7adb464092650 ]

Commit 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>") forgot
to select the correct MIPS_L1_CACHE_SHIFT for SNI RM. This breaks non
coherent DMA because of a wrong allocation alignment.

Fixes: 930beb5ac09a ("MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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