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drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions
authorJouni Högander <jouni.hogander@intel.com>
Mon, 14 Apr 2025 10:04:59 +0000 (13:04 +0300)
committerJouni Högander <jouni.hogander@intel.com>
Wed, 23 Apr 2025 09:16:26 +0000 (12:16 +0300)
commitf991ef47dad714a44d2dfbb5aed312cafc6f3e72
treecd1a96a5c6bb4088bf2bba388e337aece4d59ecbtree | snapshot
parentb23c157d46d1f1c7c96dde83dedb6e1f298fff26commit | diff
drm/i915/dmc: Add PIPEDMC_BLOCK_PKGC_SW definitions

We need PIPEDMC_BLOCK_PKGC_SW definitions to implement workaround for
underrun on idle PSR HW issue (Wa_16025596647). Add PIPEDMC_BLOCK_PKGC_SW
register definitions.

Bspec: 71265

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-5-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_dmc_regs.h diff | blob | blame | history
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