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riscv: csr: define vtype register elements
authorSergey Matyukevich <geomatsi@gmail.com>
Mon, 26 Jan 2026 04:09:57 +0000 (21:09 -0700)
committerPaul Walmsley <pjw@kernel.org>
Mon, 9 Feb 2026 22:27:33 +0000 (15:27 -0700)
commitfd515e037efb3b6300eace247e14ab2bc7e38db5
tree15fddf6b2fef1a56c873e5dd925a8a58fbe0fc18tree
parentef3ff40346db8476a9ef7269fc9d1837e7243c40commit | diff
riscv: csr: define vtype register elements

Define masks and shifts for vtype CSR according to the vector specs:
- v0.7.1 used in early T-Head cores, known as xtheadvector in the kernel
- v1.0

Signed-off-by: Sergey Matyukevich <geomatsi@gmail.com>
Reviewed-by: Andy Chiu <andybnac@gmail.com>
Tested-by: Andy Chiu <andybnac@gmail.com>
Link: https://patch.msgid.link/20251214163537.1054292-4-geomatsi@gmail.com
Signed-off-by: Paul Walmsley <pjw@kernel.org>
arch/riscv/include/asm/csr.h diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git