aarch64: Introduce prefer_advsimd_autovec to GCC 10

This patch introduces the prefer_advsimd_autovec internal tune flag that's already available on the GCC 8 and 9 branches.
It allows a CPU tuning to specify that it prefers Advanced SIMD for autovectorisation rather than SVE.
In GCC 10 onwards this can be easily adjusted through the aarch64_autovec_preference param in the options override hook.
The neoversev1_tunings struct makes use of this tuning flag

Bootstrapped and tested on aarch64-none-linux-gnu.
Confirmed that an --param aarch64-autovec-preference can override the CPU setting if the user really wishes to.

gcc/ChangeLog:

	* config/aarch64/aarch64-tuning-flags.def (prefer_advsimd_autovec): Define.
	* config/aarch64/aarch64.c (neoversev1_tunings): Use it.
	(aarch64_override_options_internal): Adjust aarch64_autovec_preference
	param when prefer_advsimd_autovec is enabled.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/advsimd_autovec_only_1.c: New test.

diff --git a/gcc/config/aarch64/aarch64-tuning-flags.def b/gcc/config/aarch64/aarch64-tuning-flags.def
index ccef3c092735c04a81d9dee890495e0b7fb09252..52c7f4763f58119f6cee1bd75410558ee733e1a8 100644 (file)
--- a/gcc/config/aarch64/aarch64-tuning-flags.def
+++ b/gcc/config/aarch64/aarch64-tuning-flags.def
@@ -46,4 +46,7 @@ AARCH64_EXTRA_TUNING_OPTION ("no_ldp_stp_qregs", NO_LDP_STP_QREGS)
 
 AARCH64_EXTRA_TUNING_OPTION ("rename_load_regs", RENAME_LOAD_REGS)
 
+/* Prefer Advanced SIMD over SVE for auto-vectorization.  */
+AARCH64_EXTRA_TUNING_OPTION ("prefer_advsimd_autovec", PREFER_ADVSIMD_AUTOVEC)
+
 #undef AARCH64_EXTRA_TUNING_OPTION

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 0fdd7cd7a8e05783a8d313ad88193cc5668debcf..9bfc99ab0900149f4fd477bcd91c43de3eb8e8c9 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1358,7 +1358,7 @@ static const struct tune_params neoversev1_tunings =
   2,   /* min_div_recip_mul_df.  */
   0,   /* max_case_values.  */
   tune_params::AUTOPREFETCHER_WEAK,    /* autoprefetcher_model.  */
-  (AARCH64_EXTRA_TUNE_NONE),   /* tune_flags.  */
+  (AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC), /* tune_flags.  */
   &generic_prefetch_tune
 };
 
@@ -14498,6 +14498,14 @@ aarch64_override_options_internal (struct gcc_options *opts)
   SET_OPTION_IF_UNSET (opts, &global_options_set,
                       param_sched_autopref_queue_depth, queue_depth);
 
+  /* If the core wants only AdvancedSIMD autovectorization, do this through
+     aarch64_autovec_preference.  If the user set it explicitly, they should
+     know what they want.  */
+  if (aarch64_tune_params.extra_tuning_flags
+      & AARCH64_EXTRA_TUNE_PREFER_ADVSIMD_AUTOVEC)
+    SET_OPTION_IF_UNSET (opts, &global_options_set,
+                        aarch64_autovec_preference, 1);
+
   /* If using Advanced SIMD only for autovectorization disable SVE vector costs
      comparison.  */
   if (aarch64_autovec_preference == 1)

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd_autovec_only_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd_autovec_only_1.c
new file mode 100644 (file)
index 0000000..7594322
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd_autovec_only_1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-O3 -mcpu=neoverse-v1" } */
+
+void __attribute__((noinline, noclone))
+vadd (int * __restrict__ dst, int * __restrict__ op1, int * __restrict__ op2, unsigned int count)
+{
+  for (int i = 0; i < count; ++i)
+  {
+    dst[i] = op1[i] + op2[i];
+  }
+}
+
+/* { dg-final { scan-assembler-not {\tadd\tz[0-9]+} } } */