riscv: dts: allwinner: d1s-t113: add hstimer node

Describe high speed timer block on Allwinner D1S-T113.

Tested on LCPI-PC-T113/F113:
- hstimer is registered as clocksource
- switching clocksource at runtime works
- after rating increase hstimer operates as a broadcast clockevent device

Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
Link: https://patch.msgid.link/20260506-h616-t113s-hstimer-v4-3-591d425863d6@mmpsystems.pl
[wens@kernel.org: change subject prefix from "arm" to "riscv"]
[wens@kernel.org: fix interrupt representation]
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>

diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index 82cc85acccb136836669430cef8bcd029503cae2..a810ad3eb2a2bfe9cfc8c60e9bfd968abf66884b 100644 (file)
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -295,6 +295,15 @@
                        clocks = <&dcxo>;
                };
 
+               hstimer@3008000 {
+                       compatible = "allwinner,sun20i-d1-hstimer";
+                       reg = <0x03008000 0x1000>;
+                       interrupts = <SOC_PERIPHERAL_IRQ(55) IRQ_TYPE_LEVEL_HIGH>,
+                                    <SOC_PERIPHERAL_IRQ(56) IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&ccu CLK_BUS_HSTIMER>;
+                       resets = <&ccu RST_BUS_HSTIMER>;
+               };
+
                wdt: watchdog@20500a0 {
                        compatible = "allwinner,sun20i-d1-wdt-reset",
                                     "allwinner,sun20i-d1-wdt";