RISC-V: Fix bugs for refine vsetvl a5, zero into vsetvl zero, zero incorrectly

Currently we support this optimization:

bb 0:
 vsetvli a5,zero,e32,mf2
bb 1:
 vsetvli a5,zero,e64,m1 --> vsetvli zero,zero,e64,m1

According RVV ISA, we can do this optimization only if both RATIO and AVL are equal.
However, current VSETVL PASS missed the check of AVL. This patch add this condition
check to fix bugs.

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (vector_infos_manager::all_same_avl_p): New function.
	(pass_vsetvl::can_refine_vsetvl_p): Add AVL check.
	(pass_vsetvl::commit_vsetvls): Ditto.
	* config/riscv/riscv-vsetvl.h: New function declaration.

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 0f2cdffb825a704decf3ffbf93f37f29027d98d0..3b84db39199b2d2b7ad9cb85a483088d6055025a 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -1440,6 +1440,29 @@ vector_infos_manager::all_same_ratio_p (sbitmap bitdata) const
   return true;
 }
 
+bool
+vector_infos_manager::all_same_avl_p (const basic_block cfg_bb,
+                                     sbitmap bitdata) const
+{
+  if (bitmap_empty_p (bitdata))
+    return false;
+
+  const auto &block_info = vector_block_infos[cfg_bb->index];
+  if (!block_info.local_dem.demand_p (DEMAND_AVL))
+    return true;
+
+  avl_info avl = block_info.local_dem.get_avl_info ();
+  unsigned int bb_index;
+  sbitmap_iterator sbi;
+
+  EXECUTE_IF_SET_IN_BITMAP (bitdata, 0, bb_index, sbi)
+  {
+    if (vector_exprs[bb_index]->get_avl_info () != avl)
+      return false;
+  }
+  return true;
+}
+
 size_t
 vector_infos_manager::expr_set_num (sbitmap bitdata) const
 {
@@ -2111,6 +2134,10 @@ pass_vsetvl::can_refine_vsetvl_p (const basic_block cfg_bb, uint8_t ratio) const
        m_vector_manager->vector_avin[cfg_bb->index]))
     return false;
 
+  if (!m_vector_manager->all_same_avl_p (
+       cfg_bb, m_vector_manager->vector_avin[cfg_bb->index]))
+    return false;
+
   size_t expr_id
     = bitmap_first_set_bit (m_vector_manager->vector_avin[cfg_bb->index]);
   if (m_vector_manager->vector_exprs[expr_id]->get_ratio () != ratio)
@@ -2225,11 +2252,11 @@ pass_vsetvl::commit_vsetvls (void)
 
              insn_info *insn = require->get_insn ();
              vector_insn_info prev_info = vector_insn_info ();
-             if (m_vector_manager->all_same_ratio_p (
-                   m_vector_manager->vector_avout[eg->src->index]))
+             sbitmap bitdata = m_vector_manager->vector_avout[eg->src->index];
+             if (m_vector_manager->all_same_ratio_p (bitdata)
+                 && m_vector_manager->all_same_avl_p (eg->dest, bitdata))
                {
-                 size_t first = bitmap_first_set_bit (
-                   m_vector_manager->vector_avout[eg->src->index]);
+                 size_t first = bitmap_first_set_bit (bitdata);
                  prev_info = *m_vector_manager->vector_exprs[first];
                }
 

diff --git a/gcc/config/riscv/riscv-vsetvl.h b/gcc/config/riscv/riscv-vsetvl.h
index dfe54d300c9b4c6dd345b497565193937e203bb3..f05b16659d3b511bed74d9b7f54c7fd77238fd52 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.h
+++ b/gcc/config/riscv/riscv-vsetvl.h
@@ -333,6 +333,9 @@ public:
   /* Get all relaxer expression id for corresponding vector info.  */
   auto_vec<size_t> get_all_available_exprs (const vector_insn_info &) const;
 
+  /* Return true if all expression set in bitmap are same AVL.  */
+  bool all_same_avl_p (const basic_block, sbitmap) const;
+
   /* Return true if all expression set in bitmap are same ratio.  */
   bool all_same_ratio_p (sbitmap) const;