airoha: update pinctrl driver to match linux-7.3

Changes are based on linux-pinctrl/for-next (future linux-7.3) branch.
Existing pinctrl patches were adapted for upstream driver.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Link: https://github.com/openwrt/openwrt/pull/24646
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/airoha/an7581/config-6.18 b/target/linux/airoha/an7581/config-6.18
index 512c7915bee19f404ae6e8db146031ae3a69642c..2a396f4656e57e8619d4dc9d8f74de3cf1178ef8 100644 (file)
--- a/target/linux/airoha/an7581/config-6.18
+++ b/target/linux/airoha/an7581/config-6.18
@@ -298,6 +298,9 @@ CONFIG_PHY_AIROHA_USB=y
 CONFIG_PHY_PACKAGE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AIROHA=y
+CONFIG_PINCTRL_AIROHA_AN7581=y
+# CONFIG_PINCTRL_AIROHA_AN7583 is not set
+# CONFIG_PINCTRL_AIROHA_EN7523 is not set
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 CONFIG_PM_GENERIC_DOMAINS=y

diff --git a/target/linux/airoha/an7583/config-6.18 b/target/linux/airoha/an7583/config-6.18
index f410dc1dcbd800547a47849b6ad6155dc257d669..9b8dd95e6ee90b9c08d352cbe69609827123a13c 100644 (file)
--- a/target/linux/airoha/an7583/config-6.18
+++ b/target/linux/airoha/an7583/config-6.18
@@ -297,6 +297,9 @@ CONFIG_PHY_AIROHA_PCIE=y
 CONFIG_PHY_PACKAGE=y
 CONFIG_PINCTRL=y
 CONFIG_PINCTRL_AIROHA=y
+# CONFIG_PINCTRL_AIROHA_AN7581 is not set
+CONFIG_PINCTRL_AIROHA_AN7583=y
+# CONFIG_PINCTRL_AIROHA_EN7523 is not set
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 CONFIG_PM_GENERIC_DOMAINS=y

diff --git a/target/linux/airoha/en7523/config-6.18 b/target/linux/airoha/en7523/config-6.18
index 3e60f19b7caf0e7553eb98439c3195b48a589d11..ecd688f2a6c367b07d71cdc399c63409965b446c 100644 (file)
--- a/target/linux/airoha/en7523/config-6.18
+++ b/target/linux/airoha/en7523/config-6.18
@@ -243,6 +243,10 @@ CONFIG_PHYLIB=y
 CONFIG_PHYLIB_LEDS=y
 CONFIG_PHY_AIROHA_PCIE=y
 CONFIG_PINCTRL=y
+CONFIG_PINCTRL_AIROHA=y
+# CONFIG_PINCTRL_AIROHA_AN7581 is not set
+# CONFIG_PINCTRL_AIROHA_AN7583 is not set
+CONFIG_PINCTRL_AIROHA_EN7523=y
 CONFIG_PM=y
 CONFIG_PM_CLK=y
 CONFIG_PREEMPT_NONE_BUILD=y

diff --git a/target/linux/airoha/patches-6.18/202-01-v7.3-pinctrl-airoha-fix-mdio-bitfield-names.patch b/target/linux/airoha/patches-6.18/202-01-v7.3-pinctrl-airoha-fix-mdio-bitfield-names.patch
new file mode 100644 (file)
index 0000000..8567a81
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-01-v7.3-pinctrl-airoha-fix-mdio-bitfield-names.patch
@@ -0,0 +1,58 @@
+From 8b64e718bd058bfbca25d1defee0ee972a85514c Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 15 Jun 2026 08:17:40 +0300
+Subject: [PATCH v11 03/37] pinctrl: airoha: fix mdio bitfield names
+
+Fix misprint in mdio bitfield name of GPIO_2ND_I2C_MODE register.
+
+While at it also fix an7583 mdio. It should use an7583 specific
+mdio bitfield.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 11 ++++++-----
+ 1 file changed, 6 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -49,7 +49,7 @@
+ 
+ /* MUX */
+ #define REG_GPIO_2ND_I2C_MODE                 0x0214
+-#define GPIO_MDC_IO_MASTER_MODE_MODE          BIT(14)
++#define GPIO_MDC_IO_MASTER_MODE_MASK          BIT(14)
+ #define GPIO_I2C_MASTER_MODE_MODE             BIT(13)
+ #define GPIO_I2S_MODE_MASK                    BIT(12)
+ #define GPIO_I2C_SLAVE_MODE_MODE              BIT(11)
+@@ -66,6 +66,7 @@
+ #define GPIO_2ND_I2C_MODE_MASK                        BIT(0)
+ 
+ #define REG_GPIO_SPI_CS1_MODE                 0x0218
++#define AN7583_GPIO_MDC_IO_MASTER_MODE_MASK   BIT(22)
+ #define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
+ #define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
+ #define GPIO_PCM_SPI_CS2_MODE_P156_MASK               BIT(19)
+@@ -1026,8 +1027,8 @@ static const struct airoha_pinctrl_func_
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_2ND_I2C_MODE,
+-                      GPIO_MDC_IO_MASTER_MODE_MODE,
+-                      GPIO_MDC_IO_MASTER_MODE_MODE
++                      GPIO_MDC_IO_MASTER_MODE_MASK,
++                      GPIO_MDC_IO_MASTER_MODE_MASK
+               },
+               .regmap[1] = {
+                       AIROHA_FUNC_MUX,
+@@ -1051,8 +1052,8 @@ static const struct airoha_pinctrl_func_
+               .regmap[1] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_MDC_IO_MASTER_MODE_MODE,
+-                      GPIO_MDC_IO_MASTER_MODE_MODE
++                      AN7583_GPIO_MDC_IO_MASTER_MODE_MASK,
++                      AN7583_GPIO_MDC_IO_MASTER_MODE_MASK
+               },
+               .regmap_size = 2,
+       },

diff --git a/target/linux/airoha/patches-6.18/202-02-v7.3-pinctrl-airoha-an7581-fix-pinconf-of-i2c_scl-i2c.patch b/target/linux/airoha/patches-6.18/202-02-v7.3-pinctrl-airoha-an7581-fix-pinconf-of-i2c_scl-i2c.patch
new file mode 100644 (file)
index 0000000..3d15eb2
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-02-v7.3-pinctrl-airoha-an7581-fix-pinconf-of-i2c_scl-i2c.patch
@@ -0,0 +1,60 @@
+From 531e07f9b70257ed127bbc3d2cd2d5100e7c1634 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 17:42:29 +0300
+Subject: [PATCH v11 04/37] pinctrl: airoha: an7581: fix pinconf of
+ i2c_scl/i2c_sda pins
+
+Pinconfs of i2c_sda/i2c_scl pins are swapped, this needs to be fixed.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -1844,8 +1844,8 @@ static const struct airoha_pinctrl_func
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+       PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+       PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+       PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+@@ -1961,8 +1961,8 @@ static const struct airoha_pinctrl_conf
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+       PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+       PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+       PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+@@ -2078,8 +2078,8 @@ static const struct airoha_pinctrl_conf
+ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+       PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+       PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+       PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+@@ -2195,8 +2195,8 @@ static const struct airoha_pinctrl_conf
+ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+       PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+       PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+       PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),

diff --git a/target/linux/airoha/patches-6.18/202-03-v7.3-pinctrl-airoha-an7583-fix-I2C0_SDA_PD-register-b.patch b/target/linux/airoha/patches-6.18/202-03-v7.3-pinctrl-airoha-an7583-fix-I2C0_SDA_PD-register-b.patch
new file mode 100644 (file)
index 0000000..ebe73c6
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-03-v7.3-pinctrl-airoha-an7583-fix-I2C0_SDA_PD-register-b.patch
@@ -0,0 +1,27 @@
+From a5178ce190f19b95420b59b49563b220f0855255 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 15 Jun 2026 08:10:28 +0300
+Subject: [PATCH v11 05/37] pinctrl: airoha: an7583: fix I2C0_SDA_PD register
+ bit order
+
+I2C1_SCL_PD and RG_I2C1_SDA_PD bits are swapped, fix it.
+
+Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -185,8 +185,8 @@
+ #define I2C_SDA_PU_MASK                               BIT(0)
+ 
+ #define REG_I2C_SDA_PD                                0x0048
+-#define AN7583_I2C1_SDA_PD_MASK                       BIT(16)
+-#define AN7583_I2C1_SCL_PD_MASK                       BIT(15)
++#define AN7583_I2C1_SCL_PD_MASK                       BIT(16)
++#define AN7583_I2C1_SDA_PD_MASK                       BIT(15)
+ #define SPI_MISO_PD_MASK                      BIT(14)
+ #define SPI_MOSI_PD_MASK                      BIT(13)
+ #define SPI_CLK_PD_MASK                               BIT(12)

diff --git a/target/linux/airoha/patches-6.18/202-04-v7.3-pinctrl-airoha-an7581-fix-mux-conf-of-pcie_reset.patch b/target/linux/airoha/patches-6.18/202-04-v7.3-pinctrl-airoha-an7581-fix-mux-conf-of-pcie_reset.patch
new file mode 100644 (file)
index 0000000..63c5a12
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-04-v7.3-pinctrl-airoha-an7581-fix-mux-conf-of-pcie_reset.patch
@@ -0,0 +1,282 @@
+From 12d2ad2443a7c666672a5d980802c0726e151d83 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Wed, 17 Jun 2026 03:02:08 +0300
+Subject: [PATCH v11 07/37] pinctrl: airoha: an7581: fix mux/conf of pcie_reset
+ pins
+
+In the an7581 case
+ * gpio47 and pcie_reset0 shares pin 60,
+ * gpio48 and pcie_reset1 shares pin 61,
+ * gpio49 and pcie_reset2 shares pin 62.
+but current driver treat them as pins 61--63. This is wrong.
+
+Also current an7581 pinmux implementation have following issues:
+ * current pcie_reset pin function actually sets corresponding
+   pins as gpios.
+ * there is no proper way to set pcie_reset pins as gpios.
+ * there is no way to set pcie_reset pins as pwm.
+
+This patch fixes above issues.
+
+WARNING:
+There is a contradiction in the Airoha documentation. AN7581 programming
+guide claims:
+ - gpio44 and pcie_reset0 shares the same pin
+ - gpio45 and pcie_reset1 shares the same pin
+ - gpio46 and pcie_reset2 shares the same pin
+While AN7581 datasheet claims:
+ - gpio47 and pcie_reset0 shares the same pin
+ - gpio48 and pcie_reset1 shares the same pin
+ - gpio49 and pcie_reset2 shares the same pin
+The datasheet should be considered as a more reliable source.
+Thanks to Benjamin Larsson for clarification.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 122 +++++++++++++++++++-----
+ 1 file changed, 97 insertions(+), 25 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -470,9 +470,9 @@ static struct pinctrl_pin_desc en7581_pi
+       PINCTRL_PIN(57, "gpio44"),
+       PINCTRL_PIN(58, "gpio45"),
+       PINCTRL_PIN(59, "gpio46"),
+-      PINCTRL_PIN(61, "pcie_reset0"),
+-      PINCTRL_PIN(62, "pcie_reset1"),
+-      PINCTRL_PIN(63, "pcie_reset2"),
++      PINCTRL_PIN(60, "pcie_reset0"),
++      PINCTRL_PIN(61, "pcie_reset1"),
++      PINCTRL_PIN(62, "pcie_reset2"),
+ };
+ 
+ static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+@@ -555,9 +555,12 @@ static const int en7581_gpio43_pins[] =
+ static const int en7581_gpio44_pins[] = { 57 };
+ static const int en7581_gpio45_pins[] = { 58 };
+ static const int en7581_gpio46_pins[] = { 59 };
+-static const int en7581_pcie_reset0_pins[] = { 61 };
+-static const int en7581_pcie_reset1_pins[] = { 62 };
+-static const int en7581_pcie_reset2_pins[] = { 63 };
++static const int en7581_gpio47_pins[] = { 60 };
++static const int en7581_gpio48_pins[] = { 61 };
++static const int en7581_gpio49_pins[] = { 62 };
++static const int en7581_pcie_reset0_pins[] = { 60 };
++static const int en7581_pcie_reset1_pins[] = { 61 };
++static const int en7581_pcie_reset2_pins[] = { 62 };
+ 
+ static const struct pingroup en7581_pinctrl_groups[] = {
+       PINCTRL_PIN_GROUP("pon", en7581_pon),
+@@ -640,6 +643,9 @@ static const struct pingroup en7581_pinc
+       PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+       PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+       PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
++      PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
++      PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
++      PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
+       PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+       PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+       PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+@@ -883,6 +889,7 @@ static const char *const an7583_pcm_spi_
+ static const char *const i2s_groups[] = { "i2s" };
+ static const char *const emmc_groups[] = { "emmc" };
+ static const char *const pnand_groups[] = { "pnand" };
++static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
+ static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
+                                                "pcie_reset2" };
+ static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
+@@ -907,7 +914,8 @@ static const char *const pwm_groups[] =
+                                         "gpio40", "gpio41",
+                                         "gpio42", "gpio43",
+                                         "gpio44", "gpio45",
+-                                        "gpio46" };
++                                        "gpio46", "gpio47",
++                                        "gpio48", "gpio49" };
+ static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
+                                                "gpio2", "gpio3",
+                                                "gpio4", "gpio5",
+@@ -1406,6 +1414,45 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
++#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      0                                       \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++static const struct airoha_pinctrl_func_group gpio_func_group[] = {
++      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET2_MASK),
++};
++
+ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+       {
+               .name = "pcie_reset0",
+@@ -1413,7 +1460,7 @@ static const struct airoha_pinctrl_func_
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+                       GPIO_PCIE_RESET0_MASK,
+-                      GPIO_PCIE_RESET0_MASK
++                      0
+               },
+               .regmap_size = 1,
+       }, {
+@@ -1422,7 +1469,7 @@ static const struct airoha_pinctrl_func_
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+                       GPIO_PCIE_RESET1_MASK,
+-                      GPIO_PCIE_RESET1_MASK
++                      0
+               },
+               .regmap_size = 1,
+       }, {
+@@ -1431,7 +1478,7 @@ static const struct airoha_pinctrl_func_
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+                       GPIO_PCIE_RESET2_MASK,
+-                      GPIO_PCIE_RESET2_MASK
++                      0
+               },
+               .regmap_size = 1,
+       },
+@@ -1484,6 +1531,24 @@ static const struct airoha_pinctrl_func_
+               .regmap_size = 1,                       \
+       }                                               \
+ 
++#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
+ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+       AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+@@ -1528,6 +1593,12 @@ static const struct airoha_pinctrl_func_
+       AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET2_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+@@ -1804,6 +1875,7 @@ static const struct airoha_pinctrl_func
+       PINCTRL_FUNC_DESC("i2s", i2s),
+       PINCTRL_FUNC_DESC("emmc", emmc),
+       PINCTRL_FUNC_DESC("pnand", pnand),
++      PINCTRL_FUNC_DESC("gpio", gpio),
+       PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+       PINCTRL_FUNC_DESC("pwm", pwm),
+       PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+@@ -1897,9 +1969,9 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
+       PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
+       PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+@@ -2014,9 +2086,9 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
+       PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
+       PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+@@ -2131,9 +2203,9 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
+       PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
+       PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+@@ -2248,9 +2320,9 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
+       PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
+       PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+@@ -2310,9 +2382,9 @@ static const struct airoha_pinctrl_conf
+ };
+ 
+ static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+-      PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+-      PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+-      PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+ };
+ 
+ static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {

diff --git a/target/linux/airoha/patches-6.18/202-05-v7.3-pinctrl-airoha-an7583-fix-muxing-of-non-gpio-def.patch b/target/linux/airoha/patches-6.18/202-05-v7.3-pinctrl-airoha-an7583-fix-muxing-of-non-gpio-def.patch
new file mode 100644 (file)
index 0000000..85b23d6
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-05-v7.3-pinctrl-airoha-an7583-fix-muxing-of-non-gpio-def.patch
@@ -0,0 +1,192 @@
+From 4b5e1e39d5cc9207ccf9e70dd4f07873ef61b175 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Tue, 16 Jun 2026 00:30:02 +0300
+Subject: [PATCH v11 09/37] pinctrl: airoha: an7583: fix muxing of non-gpio
+ default pins
+
+Current an7583 pinmux implementation have following issues:
+ * pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
+   will sets pins to gpio mode instead.
+ * there is no proper way to set pins 41--54 to gpio mode.
+ * pins 41--53 can't be actually set as pwm pins. These pins must be
+   muxed to gpio mode as well.
+
+This patch fixes above issues.
+
+Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 99 +++++++++++++++++++++----
+ 1 file changed, 86 insertions(+), 13 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -85,6 +85,18 @@
+ #define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
+ 
+ #define REG_GPIO_PON_MODE                     0x021c
++#define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
++#define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
++#define AN7583_UART_RXD_GPIO_MODE_MASK                BIT(24)
++#define AN7583_UART_TXD_GPIO_MODE_MASK                BIT(23)
++#define AN7583_SPI_MISO_GPIO_MODE_MASK                BIT(22)
++#define AN7583_SPI_MOSI_GPIO_MODE_MASK                BIT(21)
++#define AN7583_SPI_CS_GPIO_MODE_MASK          BIT(20)
++#define AN7583_SPI_CLK_GPIO_MODE_MASK         BIT(19)
++#define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
++#define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
++#define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
++#define AN7583_I2C0_SCL_GPIO_MODE_MASK                BIT(15)
+ #define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
+ #define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
+ #define GPIO_PCIE_RESET2_MASK                 BIT(12)
+@@ -783,6 +795,10 @@ static const int an7583_gpio45_pins[] =
+ static const int an7583_gpio46_pins[] = { 48 };
+ static const int an7583_gpio47_pins[] = { 49 };
+ static const int an7583_gpio48_pins[] = { 50 };
++static const int an7583_gpio49_pins[] = { 51 };
++static const int an7583_gpio50_pins[] = { 52 };
++static const int an7583_gpio51_pins[] = { 53 };
++static const int an7583_gpio52_pins[] = { 54 };
+ static const int an7583_pcie_reset0_pins[] = { 51 };
+ static const int an7583_pcie_reset1_pins[] = { 52 };
+ 
+@@ -863,6 +879,10 @@ static const struct pingroup an7583_pinc
+       PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+       PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+       PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
++      PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
++      PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
++      PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
++      PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+       PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+       PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+ };
+@@ -892,6 +912,11 @@ static const char *const pnand_groups[]
+ static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
+ static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
+                                                "pcie_reset2" };
++static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
++                                                "gpio42", "gpio43", "gpio44",
++                                                "gpio45", "gpio46", "gpio47",
++                                                "gpio48", "gpio49", "gpio50",
++                                                "gpio51", "gpio52" };
+ static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
+ static const char *const pwm_groups[] = { "gpio0", "gpio1",
+                                         "gpio2", "gpio3",
+@@ -938,7 +963,8 @@ static const char *const an7583_pwm_grou
+                                                "gpio42", "gpio43",
+                                                "gpio44", "gpio45",
+                                                "gpio46", "gpio47",
+-                                               "gpio48" };
++                                               "gpio48", "gpio49",
++                                               "gpio50", "gpio51" };
+ static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
+                                               "gpio35", "gpio42" };
+ static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
+@@ -1484,6 +1510,36 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
++static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
++      AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
++                              AN7583_I2C0_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
++                              AN7583_I2C0_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
++                              AN7583_I2C1_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
++                              AN7583_I2C1_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
++                              AN7583_SPI_CLK_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
++                              AN7583_SPI_CS_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
++                              AN7583_SPI_MOSI_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
++                              AN7583_SPI_MISO_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
++                              AN7583_UART_TXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
++                              AN7583_UART_RXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
++                              AN7583_MDC_0_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
++};
++
+ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+       {
+               .name = "pcie_reset0",
+@@ -1491,7 +1547,7 @@ static const struct airoha_pinctrl_func_
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+                       GPIO_PCIE_RESET0_MASK,
+-                      GPIO_PCIE_RESET0_MASK
++                      0
+               },
+               .regmap_size = 1,
+       }, {
+@@ -1500,7 +1556,7 @@ static const struct airoha_pinctrl_func_
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+                       GPIO_PCIE_RESET1_MASK,
+-                      GPIO_PCIE_RESET1_MASK
++                      0
+               },
+               .regmap_size = 1,
+       },
+@@ -1637,16 +1693,32 @@ static const struct airoha_pinctrl_func_
+       AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio48", GPIO48_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
++                                 AN7583_I2C0_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
++                                 AN7583_I2C0_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
++                                 AN7583_I2C1_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
++                                 AN7583_I2C1_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
++                                 AN7583_SPI_CLK_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
++                                 AN7583_SPI_CS_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
++                                 AN7583_SPI_MOSI_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
++                                 AN7583_SPI_MISO_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
++                                 AN7583_UART_TXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
++                                 AN7583_UART_RXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
++                                 AN7583_MDC_0_GPIO_MODE_MASK),
+ };
+ 
+ #define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
+@@ -1901,6 +1973,7 @@ static const struct airoha_pinctrl_func
+       PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+       PINCTRL_FUNC_DESC("emmc", emmc),
+       PINCTRL_FUNC_DESC("pnand", pnand),
++      PINCTRL_FUNC_DESC("gpio", an7583_gpio),
+       PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+       PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+       PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),

diff --git a/target/linux/airoha/patches-6.18/203-03-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN7581.patch b/target/linux/airoha/patches-6.18/202-06-v7.3-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN758.patch
similarity index 81%
rename from target/linux/airoha/patches-6.18/203-03-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN7581.patch
rename to target/linux/airoha/patches-6.18/202-06-v7.3-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN758.patch
index 46af67e7b48b0d29dc7a44356f6e5d494a764531..778ecbecd3a44a8f7936148c1fb41454047b80e6 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-03-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN7581.patch
+++ b/target/linux/airoha/patches-6.18/202-06-v7.3-pinctrl-airoha-fix-I2C1-pin-mux-config-for-AN758.patch
@@ -1,7 +1,7 @@
-From 4d69bddfbe9d8cf41e7d370472b247b6409b2735 Mon Sep 17 00:00:00 2001
+From 286ffe101d1c1f8e7f5e9bae651e90a1a04e3008 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Fri, 3 Jul 2026 22:20:28 +0200
-Subject: [PATCH] pinctrl: airoha: fix I2C1 pin mux config for AN7581
+Subject: [PATCH v11 10/37] pinctrl: airoha: fix I2C1 pin mux config for AN7581
 
 The pin mux on GPIOs 1 and 2 on AN7581 supports I2C in master and
 slave mode. When selecting I2C the according bits (bit 13 for master,
@@ -17,7 +17,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 
 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
 +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -1142,8 +1142,8 @@ static const struct airoha_pinctrl_func_
+@@ -1158,8 +1158,8 @@ static const struct airoha_pinctrl_func_
                .regmap[0] = {
                        AIROHA_FUNC_MUX,
                        REG_GPIO_2ND_I2C_MODE,

diff --git a/target/linux/airoha/patches-6.18/203-04-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch b/target/linux/airoha/patches-6.18/202-07-v7.3-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch
similarity index 66%
rename from target/linux/airoha/patches-6.18/203-04-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch
rename to target/linux/airoha/patches-6.18/202-07-v7.3-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch
index 69981285fe6487913c49a41fc016ef7e1bbc0e0d..a27f9b3c27768b44055694d6f1cb4de946a7a66d 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-04-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch
+++ b/target/linux/airoha/patches-6.18/202-07-v7.3-pinctrl-airoha-fix-I2C-pin-mux-config-for-AN7583.patch
@@ -1,7 +1,7 @@
-From 2d3405f300d79e12dbd5e259f660016f5f985b35 Mon Sep 17 00:00:00 2001
+From 86ab05718e4070f319a4ea7121694d298b59b829 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Fri, 3 Jul 2026 22:20:28 +0200
-Subject: [PATCH] pinctrl: airoha: fix I2C pin mux config for AN7583
+Subject: [PATCH v11 12/37] pinctrl: airoha: fix I2C pin mux config for AN7583
 
 On AN7583 both I2C busses have a pin sharing with GPIO. Also the pin mux
 setting is done in REG_GPIO_PON_MODE instead of REG_GPIO_2ND_I2C_MODE.
@@ -11,23 +11,12 @@ groups must support i2c0 and i2c1.
 
 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 ---
- drivers/pinctrl/airoha/pinctrl-airoha.c | 29 ++++++++++++++++++++++++-
- 1 file changed, 28 insertions(+), 1 deletion(-)
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 25 ++++++++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
 
 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
 +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -85,6 +85,10 @@
- 
- #define REG_GPIO_PON_MODE                     0x021c
- #define AN7583_GPIO_MODE_MASK                 (GENMASK(22, 15) | GENMASK(26, 25))
-+#define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
-+#define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
-+#define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
-+#define AN7583_I2C0_SCL_GPIO_MODE_MASK                BIT(15)
- #define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
- #define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
- #define GPIO_PCIE_RESET2_MASK                 BIT(12)
-@@ -880,6 +884,7 @@ static const char *const uart_groups[] =
+@@ -896,6 +896,7 @@ static const char *const uart_groups[] =
                                           "hsuart_cts_rts", "uart4",
                                           "uart5" };
  static const char *const i2c_groups[] = { "i2c1" };
@@ -35,7 +24,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
  static const char *const pcm_groups[] = { "pcm1", "pcm2" };
  static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-@@ -1149,6 +1154,28 @@ static const struct airoha_pinctrl_func_
+@@ -1165,6 +1166,28 @@ static const struct airoha_pinctrl_func_
        },
  };
  
@@ -64,7 +53,7 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  static const struct airoha_pinctrl_func_group jtag_func_group[] = {
        {
                .name = "jtag_udi",
-@@ -1872,7 +1899,7 @@ static const struct airoha_pinctrl_func
+@@ -1966,7 +1989,7 @@ static const struct airoha_pinctrl_func
        PINCTRL_FUNC_DESC("sipo", sipo),
        PINCTRL_FUNC_DESC("mdio", an7583_mdio),
        PINCTRL_FUNC_DESC("uart", uart),

diff --git a/target/linux/airoha/patches-6.18/203-05-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch b/target/linux/airoha/patches-6.18/202-08-v7.3-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch
similarity index 68%
rename from target/linux/airoha/patches-6.18/203-05-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch
rename to target/linux/airoha/patches-6.18/202-08-v7.3-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch
index 35ebaebe35995e48f5e5a98f9041298e9e6fe992..1b4f6d7fc4d44a5ac03611a3321316e512c609ab 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-05-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch
+++ b/target/linux/airoha/patches-6.18/202-08-v7.3-pinctrl-airoha-fix-AN7583-MDIO-pin-mux-config.patch
@@ -1,7 +1,7 @@
-From 614954a5df7505f68727ea920bce362c58a1fbdb Mon Sep 17 00:00:00 2001
+From 2d618de8e83469dbd9e5c32aa9a55e3844530a1f Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Sat, 4 Jul 2026 00:14:10 +0200
-Subject: [PATCH] pinctrl: airoha: fix AN7583 MDIO pin mux config
+Subject: [PATCH v11 13/37] pinctrl: airoha: fix AN7583 MDIO pin mux config
 
 an7583_mdio_pins[] pointed at pins 43/44 (I2C1_SDA/I2C1_SCL) instead of
 pins 53/54 (MDC_0/MDIO_0 respectively GPIO 51/52). Also the MDIO function
@@ -21,25 +21,25 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 
 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
 +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -85,6 +85,8 @@
- 
- #define REG_GPIO_PON_MODE                     0x021c
- #define AN7583_GPIO_MODE_MASK                 (GENMASK(22, 15) | GENMASK(26, 25))
-+#define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
-+#define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
- #define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
- #define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
- #define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
-@@ -720,7 +722,7 @@ static const int an7583_pon_tod_1pps_pin
+@@ -724,7 +724,8 @@ static const int an7583_pon_tod_1pps_pin
  static const int an7583_gsw_tod_1pps_pins[] = { 32 };
  static const int an7583_sipo_pins[] = { 34, 35 };
  static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
 -static const int an7583_mdio_pins[] = { 43, 44 };
 +static const int an7583_mdio_pins[] = { 53, 54 };
++static const int an7583_mdio1_pins[] = { 43, 44 };
  static const int an7583_uart2_pins[] = { 34, 35 };
  static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
  static const int an7583_hsuart_pins[] = { 30, 31 };
-@@ -1069,16 +1071,10 @@ static const struct airoha_pinctrl_func_
+@@ -809,6 +810,7 @@ static const struct pingroup an7583_pinc
+       PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+       PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+       PINCTRL_PIN_GROUP("mdio", an7583_mdio),
++      PINCTRL_PIN_GROUP("mdio1", an7583_mdio1),
+       PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+       PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+       PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+@@ -1081,16 +1083,10 @@ static const struct airoha_pinctrl_func_
                .regmap[0] = {
                        AIROHA_FUNC_MUX,
                        REG_GPIO_PON_MODE,
@@ -51,8 +51,8 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 -              .regmap[1] = {
 -                      AIROHA_FUNC_MUX,
 -                      REG_GPIO_SPI_CS1_MODE,
--                      GPIO_MDC_IO_MASTER_MODE_MODE,
--                      GPIO_MDC_IO_MASTER_MODE_MODE
+-                      AN7583_GPIO_MDC_IO_MASTER_MODE_MASK,
+-                      AN7583_GPIO_MDC_IO_MASTER_MODE_MASK
 -              },
 -              .regmap_size = 2,
 +              .regmap_size = 1,

diff --git a/target/linux/airoha/patches-6.18/202-09-v7.3-pinctrl-airoha-an7583-fix-spi-group-pins.patch b/target/linux/airoha/patches-6.18/202-09-v7.3-pinctrl-airoha-an7583-fix-spi-group-pins.patch
new file mode 100644 (file)
index 0000000..1b8e671
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-09-v7.3-pinctrl-airoha-an7583-fix-spi-group-pins.patch
@@ -0,0 +1,26 @@
+From 3a8b48d8a63a3e93d5307148bc93d49eb7c18c27 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 3 Aug 2026 01:02:46 +0300
+Subject: [PATCH v11 14/37] pinctrl: airoha: an7583: fix spi group pins
+
+pcm pins were used insted of spi pins. This patch fixes an issue.
+
+Thanks to Daniel Schwierzeck for noticing it.
+
+Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -739,7 +739,7 @@ static const int an7583_jtag_udi_pins[]
+ static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+ static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+ static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+-static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
++static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
+ static const int an7583_spi_quad_pins[] = { 25, 26 };
+ static const int an7583_spi_cs1_pins[] = { 27 };
+ static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };

diff --git a/target/linux/airoha/patches-6.18/202-10-v7.3-pinctrl-airoha-add-missed-get_direction-function.patch b/target/linux/airoha/patches-6.18/202-10-v7.3-pinctrl-airoha-add-missed-get_direction-function.patch
new file mode 100644 (file)
index 0000000..7c7cf98
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-10-v7.3-pinctrl-airoha-add-missed-get_direction-function.patch
@@ -0,0 +1,108 @@
+From f652e4cfd3421da7eb0d959d362e8a455a12034c Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 03:51:42 +0300
+Subject: [PATCH v11 15/37] pinctrl: airoha: add missed get_direction()
+ function for gpio_chip
+
+This patch adds missed get_direction() function for gpio_chip.
+Also it reimplements pinconf's get_direction() function using
+newly defined function.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 50 +++++++++++++++++--------
+ 1 file changed, 34 insertions(+), 16 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2523,6 +2523,22 @@ static int airoha_gpio_get(struct gpio_c
+       return err ? err : !!(val & BIT(pin));
+ }
+ 
++static int airoha_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
++{
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
++      u32 val, mask;
++      u8 index;
++      int err;
++
++      index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
++      err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
++      if (err)
++              return err;
++
++      mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN));
++      return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
++}
++
+ static int airoha_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned int gpio, int value)
+ {
+@@ -2656,19 +2672,13 @@ static int airoha_pinctrl_add_gpiochip(s
+       struct device *dev = &pdev->dev;
+       int irq, err;
+ 
+-      chip->data = gpio_data_regs;
+-      chip->dir = gpio_dir_regs;
+-      chip->out = gpio_out_regs;
+-      chip->status = irq_status_regs;
+-      chip->level = irq_level_regs;
+-      chip->edge = irq_edge_regs;
+-
+       gc->parent = dev;
+       gc->label = dev_name(dev);
+       gc->request = gpiochip_generic_request;
+       gc->free = gpiochip_generic_free;
+       gc->direction_input = pinctrl_gpio_direction_input;
+       gc->direction_output = airoha_gpio_direction_output;
++      gc->get_direction = airoha_gpio_get_direction;
+       gc->set = airoha_gpio_set;
+       gc->get = airoha_gpio_get;
+       gc->base = -1;
+@@ -2878,21 +2888,18 @@ static int airoha_pinctrl_set_conf(struc
+ static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
+ {
+       struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+-      u32 val, mask;
+-      int err, pin;
+-      u8 index;
++      int ret, pin;
+ 
+       pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p);
+       if (pin < 0)
+               return pin;
+ 
+-      index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
+-      err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
+-      if (err)
+-              return err;
++      ret = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, pin);
++      if (ret < 0)
++              return ret;
+ 
+-      mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
+-      return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
++      return ret == GPIO_LINE_DIRECTION_OUT ?
++             PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE;
+ }
+ 
+ static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev,
+@@ -3138,6 +3145,17 @@ static int airoha_pinctrl_probe(struct p
+       pinctrl->desc.pins = data->pins;
+       pinctrl->desc.npins = data->num_pins;
+ 
++      /*
++       * some pinctrl operations (ex: get_direction) might use gpio registers
++       * before gpio chip abstraction will be completely initialized.
++       */
++      pinctrl->gpiochip.data = gpio_data_regs;
++      pinctrl->gpiochip.dir = gpio_dir_regs;
++      pinctrl->gpiochip.out = gpio_out_regs;
++      pinctrl->gpiochip.status = irq_status_regs;
++      pinctrl->gpiochip.level = irq_level_regs;
++      pinctrl->gpiochip.edge = irq_edge_regs;
++
+       err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
+                                            pinctrl, &pinctrl->ctrl);
+       if (err)

diff --git a/target/linux/airoha/patches-6.18/202-11-v7.3-pinctrl-airoha-add-set_direction-helper-for-gpio.patch b/target/linux/airoha/patches-6.18/202-11-v7.3-pinctrl-airoha-add-set_direction-helper-for-gpio.patch
new file mode 100644 (file)
index 0000000..7badd49
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-11-v7.3-pinctrl-airoha-add-set_direction-helper-for-gpio.patch
@@ -0,0 +1,103 @@
+From 4b3f986d1f76d4234b27850b44e26492bf974b23 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 04:20:42 +0300
+Subject: [PATCH v11 16/37] pinctrl: airoha: add set_direction() helper for
+ gpio_chip
+
+The patch creates set_direction() helper for gpio_chip abstraction.
+It also implements/reimplements some function using newly defined
+helper.
+
+This is cosmetic patch used to place gpio_chip specific code together.
+No functional changes.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 52 ++++++++++++++++---------
+ 1 file changed, 34 insertions(+), 18 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2539,12 +2539,42 @@ static int airoha_gpio_get_direction(str
+       return val & mask ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
+ }
+ 
++static int airoha_gpio_set_direction(struct gpio_chip *chip, unsigned int gpio,
++                                   bool input)
++{
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
++      u32 mask, index;
++      int err;
++
++      /* set output enable */
++      mask = BIT(gpio % AIROHA_PIN_BANK_SIZE);
++      index = gpio / AIROHA_PIN_BANK_SIZE;
++      err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
++                               mask, !input ? mask : 0);
++      if (err)
++              return err;
++
++      /* set direction */
++      mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN));
++      index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
++
++      return regmap_update_bits(pinctrl->regmap,
++                                pinctrl->gpiochip.dir[index], mask,
++                                !input ? mask : 0);
++}
++
++static int airoha_gpio_direction_input(struct gpio_chip *chip,
++                                     unsigned int gpio)
++{
++      return airoha_gpio_set_direction(chip, gpio, true);
++}
++
+ static int airoha_gpio_direction_output(struct gpio_chip *chip,
+                                       unsigned int gpio, int value)
+ {
+       int err;
+ 
+-      err = pinctrl_gpio_direction_output(chip, gpio);
++      err = airoha_gpio_set_direction(chip, gpio, false);
+       if (err)
+               return err;
+ 
+@@ -2676,7 +2706,7 @@ static int airoha_pinctrl_add_gpiochip(s
+       gc->label = dev_name(dev);
+       gc->request = gpiochip_generic_request;
+       gc->free = gpiochip_generic_free;
+-      gc->direction_input = pinctrl_gpio_direction_input;
++      gc->direction_input = airoha_gpio_direction_input;
+       gc->direction_output = airoha_gpio_direction_output;
+       gc->get_direction = airoha_gpio_get_direction;
+       gc->set = airoha_gpio_set;
+@@ -2761,27 +2791,13 @@ static int airoha_pinmux_set_direction(s
+                                       unsigned int p, bool input)
+ {
+       struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+-      u32 mask, index;
+-      int err, pin;
++      int pin;
+ 
+       pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
+       if (pin < 0)
+               return pin;
+ 
+-      /* set output enable */
+-      mask = BIT(pin % AIROHA_PIN_BANK_SIZE);
+-      index = pin / AIROHA_PIN_BANK_SIZE;
+-      err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
+-                               mask, !input ? mask : 0);
+-      if (err)
+-              return err;
+-
+-      /* set direction */
+-      mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
+-      index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
+-      return regmap_update_bits(pinctrl->regmap,
+-                                pinctrl->gpiochip.dir[index], mask,
+-                                !input ? mask : 0);
++      return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, pin, input);
+ }
+ 
+ static const struct pinmux_ops airoha_pmxops = {

diff --git a/target/linux/airoha/patches-6.18/202-12-v7.3-pinctrl-airoha-minor-improvements.patch b/target/linux/airoha/patches-6.18/202-12-v7.3-pinctrl-airoha-minor-improvements.patch
new file mode 100644 (file)
index 0000000..73a165d
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-12-v7.3-pinctrl-airoha-minor-improvements.patch
@@ -0,0 +1,119 @@
+From 3acf1bd98f274a44cb3bd5c78abb98b5c2bd3a03 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Wed, 29 Jul 2026 15:44:10 +0300
+Subject: [PATCH v11 17/37] pinctrl: airoha: minor improvements
+
+Changes:
+ * use field_get() macro instead of direct bit operations
+ * improve error handling
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 56 +++++++++++++++++++------
+ 1 file changed, 43 insertions(+), 13 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2842,7 +2842,7 @@ static int airoha_pinctrl_get_conf(struc
+       if (regmap_read(pinctrl->chip_scu, reg->offset, val))
+               return -EINVAL;
+ 
+-      *val = (*val & reg->mask) >> __ffs(reg->mask);
++      *val = field_get(reg->mask, *val);
+ 
+       return 0;
+ }
+@@ -2864,7 +2864,7 @@ static int airoha_pinctrl_set_conf(struc
+ 
+ 
+       if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask,
+-                              val << __ffs(reg->mask)))
++                             field_prep(reg->mask, val)))
+               return -EINVAL;
+ 
+       return 0;
+@@ -2996,7 +2996,7 @@ static int airoha_pinconf_set(struct pin
+                             unsigned int num_configs)
+ {
+       struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+-      int i;
++      int i, err;
+ 
+       for (i = 0; i < num_configs; i++) {
+               u32 param = pinconf_to_config_param(configs[i]);
+@@ -3004,16 +3004,35 @@ static int airoha_pinconf_set(struct pin
+ 
+               switch (param) {
+               case PIN_CONFIG_BIAS_DISABLE:
+-                      airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
+-                      airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
++                      err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
++                      if (err)
++                              return err;
++
++                      err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
++                      if (err)
++                              return err;
++
+                       break;
++
+               case PIN_CONFIG_BIAS_PULL_UP:
+-                      airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
+-                      airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1);
++                      err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0);
++                      if (err)
++                              return err;
++
++                      err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1);
++                      if (err)
++                              return err;
++
+                       break;
+               case PIN_CONFIG_BIAS_PULL_DOWN:
+-                      airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1);
+-                      airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
++                      err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1);
++                      if (err)
++                              return err;
++
++                      err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0);
++                      if (err)
++                              return err;
++
+                       break;
+               case PIN_CONFIG_DRIVE_STRENGTH: {
+                       u32 e2 = 0, e4 = 0;
+@@ -3035,18 +3054,29 @@ static int airoha_pinconf_set(struct pin
+                               return -EINVAL;
+                       }
+ 
+-                      airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2);
+-                      airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4);
++                      err = airoha_pinctrl_set_drive_e2_conf(pinctrl,
++                                                             pin, e2);
++                      if (err)
++                              return err;
++
++                      err = airoha_pinctrl_set_drive_e4_conf(pinctrl,
++                                                             pin, e4);
++                      if (err)
++                              return err;
++
+                       break;
+               }
+               case PIN_CONFIG_DRIVE_OPEN_DRAIN:
+-                      airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg);
++                      err = airoha_pinctrl_set_pcie_rst_od_conf(pinctrl,
++                                                                pin, !!arg);
++                      if (err)
++                              return err;
++
+                       break;
+               case PIN_CONFIG_OUTPUT_ENABLE:
+               case PIN_CONFIG_INPUT_ENABLE:
+               case PIN_CONFIG_LEVEL: {
+                       bool input = param == PIN_CONFIG_INPUT_ENABLE;
+-                      int err;
+ 
+                       err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin,
+                                                         input);

diff --git a/target/linux/airoha/patches-6.18/202-13-v7.3-pinctrl-airoha-fix-getting-gpiochip-pinctrl-poin.patch b/target/linux/airoha/patches-6.18/202-13-v7.3-pinctrl-airoha-fix-getting-gpiochip-pinctrl-poin.patch
new file mode 100644 (file)
index 0000000..5a32c63
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-13-v7.3-pinctrl-airoha-fix-getting-gpiochip-pinctrl-poin.patch
@@ -0,0 +1,95 @@
+From a610e3afa774cfb8dedb6cdf741c78bd43105c50 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Sun, 26 Jul 2026 22:49:35 +0300
+Subject: [PATCH v11 18/37] pinctrl: airoha: fix getting gpiochip/pinctrl
+ pointers in the IRQ handling code
+
+airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions
+impements brain damaged logic to retrieve gpiochip and pinctrl pointers.
+
+Details:
+
+    gpiochip = irq_data_get_irq_chip_data(data);
+
+will initialize gpiochip variable with data->chip_data value. This value
+initialized inside gpiochip_irq_map() function
+
+    static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
+                               irq_hw_number_t hwirq)
+    {
+       struct gpio_chip *gc = d->host_data;
+        ...
+       irq_set_chip_data(irq, gc);
+       ...
+    }
+
+Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be
+initialized with a pointer to a variable of 'struct gpio_chip' type.
+
+Luckily, gpio_chip is the first element of airoha_pinctrl_gpiochip, so
+gpiochip pointer will get a correct value.
+
+This patch implements correct logic of getting gpiochip and pinctrl
+pointers.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 20 +++++++++-----------
+ 1 file changed, 9 insertions(+), 11 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2584,18 +2584,17 @@ static int airoha_gpio_direction_output(
+ /* irq callbacks */
+ static void airoha_irq_unmask(struct irq_data *data)
+ {
++      struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
++      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
+       u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+-      struct airoha_pinctrl_gpiochip *gpiochip;
+-      struct airoha_pinctrl *pinctrl;
+       u32 val = BIT(2 * offset);
+ 
+-      gpiochip = irq_data_get_irq_chip_data(data);
+       if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
+               return;
+ 
+-      pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
+       switch (gpiochip->irq_type[data->hwirq]) {
+       case IRQ_TYPE_LEVEL_LOW:
+               val = val << 1;
+@@ -2621,14 +2620,12 @@ static void airoha_irq_unmask(struct irq
+ 
+ static void airoha_irq_mask(struct irq_data *data)
+ {
++      struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
++      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
+       u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+-      struct airoha_pinctrl_gpiochip *gpiochip;
+-      struct airoha_pinctrl *pinctrl;
+-
+-      gpiochip = irq_data_get_irq_chip_data(data);
+-      pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip);
+ 
+       regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
+       regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
+@@ -2636,9 +2633,10 @@ static void airoha_irq_mask(struct irq_d
+ 
+ static int airoha_irq_type(struct irq_data *data, unsigned int type)
+ {
+-      struct airoha_pinctrl_gpiochip *gpiochip;
++      struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
++      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
+ 
+-      gpiochip = irq_data_get_irq_chip_data(data);
+       if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+               return -EINVAL;
+ 

diff --git a/target/linux/airoha/patches-6.18/202-14-v7.3-pinctrl-airoha-add-missed-IRQ-resource-helpers.patch b/target/linux/airoha/patches-6.18/202-14-v7.3-pinctrl-airoha-add-missed-IRQ-resource-helpers.patch
new file mode 100644 (file)
index 0000000..88ebdea
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-14-v7.3-pinctrl-airoha-add-missed-IRQ-resource-helpers.patch
@@ -0,0 +1,26 @@
+From c25b70e4d673c673dc12ab7ac05309e7b27a8a59 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 05:13:15 +0300
+Subject: [PATCH v11 19/37] pinctrl: airoha: add missed IRQ resource helpers
+
+Without hooking .irq_request_resources, gpiolib cannot set
+GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow
+userspace or another driver to reconfigure an active IRQ pin as an output
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2689,6 +2689,7 @@ static const struct irq_chip airoha_gpio
+       .irq_mask_ack = airoha_irq_mask,
+       .irq_set_type = airoha_irq_type,
+       .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
++      GPIOCHIP_IRQ_RESOURCE_HELPERS,
+ };
+ 
+ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,

diff --git a/target/linux/airoha/patches-6.18/202-15-v7.3-pinctrl-airoha-fix-IRQ-mask-unmask-code.patch b/target/linux/airoha/patches-6.18/202-15-v7.3-pinctrl-airoha-fix-IRQ-mask-unmask-code.patch
new file mode 100644 (file)
index 0000000..9a1bf9e
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-15-v7.3-pinctrl-airoha-fix-IRQ-mask-unmask-code.patch
@@ -0,0 +1,37 @@
+From 912d05214e17739192d2a30ef262225ec4f88839 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 05:08:18 +0300
+Subject: [PATCH v11 20/37] pinctrl: airoha: fix IRQ mask/unmask code
+
+When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call
+gpiochip_enable_irq() and airoha_irq_mask() must call
+gpiochip_disable_irq(). Without these calls, gpiolib never sets the
+GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing,
+gpiod_direction_output() will not realize the pin is actively used
+as an interrupt.
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2595,6 +2595,7 @@ static void airoha_irq_unmask(struct irq
+       if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
+               return;
+ 
++      gpiochip_enable_irq(gc, irqd_to_hwirq(data));
+       switch (gpiochip->irq_type[data->hwirq]) {
+       case IRQ_TYPE_LEVEL_LOW:
+               val = val << 1;
+@@ -2629,6 +2630,7 @@ static void airoha_irq_mask(struct irq_d
+ 
+       regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
+       regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
++      gpiochip_disable_irq(gc, irqd_to_hwirq(data));
+ }
+ 
+ static int airoha_irq_type(struct irq_data *data, unsigned int type)

diff --git a/target/linux/airoha/patches-6.18/202-16-v7.3-pinctrl-airoha-fix-edge-triggered-interrupts-han.patch b/target/linux/airoha/patches-6.18/202-16-v7.3-pinctrl-airoha-fix-edge-triggered-interrupts-han.patch
new file mode 100644 (file)
index 0000000..58e040e
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-16-v7.3-pinctrl-airoha-fix-edge-triggered-interrupts-han.patch
@@ -0,0 +1,105 @@
+From 486348492dc87c9710c35265bd6b0c4b795bd837 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 05:27:35 +0300
+Subject: [PATCH v11 21/37] pinctrl: airoha: fix edge-triggered interrupts
+ handling
+
+Edge-triggered interrupts are handled incorrectly because of
+ * no irq_ack() handler was defined,
+ * no handle_level_irq() handler was used,
+
+This patch probably fixes an issue
+
+Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Acked-by: Lorenzo Bianconi <lorenzo@kernel.org>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 38 +++++++++++++++++++++----
+ 1 file changed, 33 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -2628,11 +2628,28 @@ static void airoha_irq_mask(struct irq_d
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+ 
++      if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
++              return;
++
+       regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
+       regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
+       gpiochip_disable_irq(gc, irqd_to_hwirq(data));
+ }
+ 
++static void airoha_irq_ack(struct irq_data *data)
++{
++      struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
++      struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
++      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
++      u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
++      u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
++
++      if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
++              return;
++
++      regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
++}
++
+ static int airoha_irq_type(struct irq_data *data, unsigned int type)
+ {
+       struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+@@ -2642,13 +2659,25 @@ static int airoha_irq_type(struct irq_da
+       if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
+               return -EINVAL;
+ 
++      if (type == IRQ_TYPE_NONE) {
++              gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
++              irq_set_handler_locked(data, handle_bad_irq);
++
++              return 0;
++      }
++
+       if (type == IRQ_TYPE_PROBE) {
+               if (gpiochip->irq_type[data->hwirq])
+                       return 0;
+ 
+-              type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
++              type = IRQ_TYPE_EDGE_BOTH;
+       }
++
+       gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
++      if (type & IRQ_TYPE_EDGE_BOTH)
++              irq_set_handler_locked(data, handle_edge_irq);
++      else
++              irq_set_handler_locked(data, handle_level_irq);
+ 
+       return 0;
+ }
+@@ -2673,8 +2702,7 @@ static irqreturn_t airoha_irq_handler(in
+               for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) {
+                       u32 offset = irq + i * AIROHA_PIN_BANK_SIZE;
+ 
+-                      generic_handle_irq(irq_find_mapping(girq->domain,
+-                                                          offset));
++                      generic_handle_domain_irq(girq->domain, offset);
+                       regmap_write(pinctrl->regmap,
+                                    pinctrl->gpiochip.status[i], BIT(irq));
+               }
+@@ -2688,7 +2716,7 @@ static const struct irq_chip airoha_gpio
+       .name = "airoha-gpio-irq",
+       .irq_unmask = airoha_irq_unmask,
+       .irq_mask = airoha_irq_mask,
+-      .irq_mask_ack = airoha_irq_mask,
++      .irq_ack = airoha_irq_ack,
+       .irq_set_type = airoha_irq_type,
+       .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE,
+       GPIOCHIP_IRQ_RESOURCE_HELPERS,
+@@ -2716,7 +2744,7 @@ static int airoha_pinctrl_add_gpiochip(s
+       gc->ngpio = AIROHA_NUM_PINS;
+ 
+       girq->default_type = IRQ_TYPE_NONE;
+-      girq->handler = handle_simple_irq;
++      girq->handler = handle_bad_irq;
+       gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip);
+ 
+       irq = platform_get_irq(pdev, 0);

diff --git a/target/linux/airoha/patches-6.18/202-17-v7.3-pinctrl-airoha-remove-not-needed-irq_type-array.patch b/target/linux/airoha/patches-6.18/202-17-v7.3-pinctrl-airoha-remove-not-needed-irq_type-array.patch
new file mode 100644 (file)
index 0000000..40786eb
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-17-v7.3-pinctrl-airoha-remove-not-needed-irq_type-array.patch
@@ -0,0 +1,89 @@
+From be711910de030e842a15a6e21f89fa38923be9e4 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 27 Jul 2026 08:54:02 +0300
+Subject: [PATCH v11 22/37] pinctrl: airoha: remove not needed irq_type[] array
+
+irq_type[] array inside airoha_pinctrl_gpiochip structure is not
+actually necessary. Use trigger type from 'struct irq_data' instead.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 22 ++++++++--------------
+ 1 file changed, 8 insertions(+), 14 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -383,8 +383,6 @@ struct airoha_pinctrl_gpiochip {
+       const u32 *status;
+       const u32 *level;
+       const u32 *edge;
+-
+-      u32 irq_type[AIROHA_NUM_PINS];
+ };
+ 
+ struct airoha_pinctrl_confs_info {
+@@ -2592,11 +2590,11 @@ static void airoha_irq_unmask(struct irq
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+       u32 val = BIT(2 * offset);
+ 
+-      if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)))
++      if (WARN_ON_ONCE(data->hwirq >= AIROHA_NUM_PINS))
+               return;
+ 
+       gpiochip_enable_irq(gc, irqd_to_hwirq(data));
+-      switch (gpiochip->irq_type[data->hwirq]) {
++      switch (irqd_get_trigger_type(data)) {
+       case IRQ_TYPE_LEVEL_LOW:
+               val = val << 1;
+               fallthrough;
+@@ -2628,7 +2626,7 @@ static void airoha_irq_mask(struct irq_d
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+ 
+-      if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
++      if (data->hwirq >= AIROHA_NUM_PINS)
+               return;
+ 
+       regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
+@@ -2644,7 +2642,7 @@ static void airoha_irq_ack(struct irq_da
+       u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
+       u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
+ 
+-      if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
++      if (data->hwirq >= AIROHA_NUM_PINS)
+               return;
+ 
+       regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
+@@ -2652,28 +2650,24 @@ static void airoha_irq_ack(struct irq_da
+ 
+ static int airoha_irq_type(struct irq_data *data, unsigned int type)
+ {
+-      struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+-      struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+-      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
+-
+-      if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))
++      if (data->hwirq >= AIROHA_NUM_PINS)
+               return -EINVAL;
+ 
+       if (type == IRQ_TYPE_NONE) {
+-              gpiochip->irq_type[data->hwirq] = IRQ_TYPE_NONE;
++              irqd_set_trigger_type(data, type);
+               irq_set_handler_locked(data, handle_bad_irq);
+ 
+               return 0;
+       }
+ 
+       if (type == IRQ_TYPE_PROBE) {
+-              if (gpiochip->irq_type[data->hwirq])
++              if (irqd_get_trigger_type(data))
+                       return 0;
+ 
+               type = IRQ_TYPE_EDGE_BOTH;
+       }
+ 
+-      gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK;
++      irqd_set_trigger_type(data, type);
+       if (type & IRQ_TYPE_EDGE_BOTH)
+               irq_set_handler_locked(data, handle_edge_irq);
+       else

diff --git a/target/linux/airoha/patches-6.18/202-18-v7.3-pinctrl-airoha-statically-allocate-gpio-regs-str.patch b/target/linux/airoha/patches-6.18/202-18-v7.3-pinctrl-airoha-statically-allocate-gpio-regs-str.patch
new file mode 100644 (file)
index 0000000..125de4f
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-18-v7.3-pinctrl-airoha-statically-allocate-gpio-regs-str.patch
@@ -0,0 +1,274 @@
+From 7599a177c724595dc3b0f7d56110af4f885b9cb1 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Wed, 29 Jul 2026 05:51:14 +0300
+Subject: [PATCH v11 23/37] pinctrl: airoha: statically allocate gpio regs
+ structure
+
+just a small refactoring to collect all gpio register information
+in the one statically allocated structure.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 92 ++++++++++++-------------
+ 1 file changed, 46 insertions(+), 46 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -303,6 +303,17 @@
+ #define AIROHA_PIN_BANK_SIZE                  (AIROHA_NUM_PINS / 2)
+ #define AIROHA_REG_GPIOCTRL_NUM_PIN           (AIROHA_NUM_PINS / 4)
+ 
++struct airoha_gpiochip_regs {
++      /* gpio */
++      const u32 *data;
++      const u32 *dir;
++      const u32 *out;
++      /* irq */
++      const u32 *status;
++      const u32 *level;
++      const u32 *edge;
++};
++
+ static const u32 gpio_data_regs[] = {
+       REG_GPIO_DATA,
+       REG_GPIO_DATA1
+@@ -339,6 +350,15 @@ static const u32 irq_edge_regs[] = {
+       REG_GPIO_INT_EDGE3
+ };
+ 
++static struct airoha_gpiochip_regs airoha_gpiochip_regs = {
++      .data = gpio_data_regs,
++      .dir = gpio_dir_regs,
++      .out = gpio_out_regs,
++      .status = irq_status_regs,
++      .level = irq_level_regs,
++      .edge = irq_edge_regs,
++};
++
+ struct airoha_pinctrl_reg {
+       u32 offset;
+       u32 mask;
+@@ -372,19 +392,6 @@ struct airoha_pinctrl_conf {
+       struct airoha_pinctrl_reg reg;
+ };
+ 
+-struct airoha_pinctrl_gpiochip {
+-      struct gpio_chip chip;
+-
+-      /* gpio */
+-      const u32 *data;
+-      const u32 *dir;
+-      const u32 *out;
+-      /* irq */
+-      const u32 *status;
+-      const u32 *level;
+-      const u32 *edge;
+-};
+-
+ struct airoha_pinctrl_confs_info {
+       const struct airoha_pinctrl_conf *confs;
+       unsigned int num_confs;
+@@ -411,7 +418,8 @@ struct airoha_pinctrl {
+       struct regmap *chip_scu;
+       struct regmap *regmap;
+ 
+-      struct airoha_pinctrl_gpiochip gpiochip;
++      struct gpio_chip gpiochip;
++      struct airoha_gpiochip_regs *gpio_regs;
+ };
+ 
+ struct airoha_pinctrl_match_data {
+@@ -2504,7 +2512,7 @@ static int airoha_gpio_set(struct gpio_c
+       u8 index = gpio / AIROHA_PIN_BANK_SIZE;
+ 
+       return regmap_update_bits(pinctrl->regmap,
+-                                pinctrl->gpiochip.data[index],
++                                pinctrl->gpio_regs->data[index],
+                                 BIT(offset), value ? BIT(offset) : 0);
+ }
+ 
+@@ -2516,7 +2524,7 @@ static int airoha_gpio_get(struct gpio_c
+       int err;
+ 
+       err = regmap_read(pinctrl->regmap,
+-                        pinctrl->gpiochip.data[index], &val);
++                        pinctrl->gpio_regs->data[index], &val);
+ 
+       return err ? err : !!(val & BIT(pin));
+ }
+@@ -2529,7 +2537,8 @@ static int airoha_gpio_get_direction(str
+       int err;
+ 
+       index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
+-      err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val);
++      err = regmap_read(pinctrl->regmap,
++                        pinctrl->gpio_regs->dir[index], &val);
+       if (err)
+               return err;
+ 
+@@ -2547,7 +2556,8 @@ static int airoha_gpio_set_direction(str
+       /* set output enable */
+       mask = BIT(gpio % AIROHA_PIN_BANK_SIZE);
+       index = gpio / AIROHA_PIN_BANK_SIZE;
+-      err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index],
++      err = regmap_update_bits(pinctrl->regmap,
++                               pinctrl->gpio_regs->out[index],
+                                mask, !input ? mask : 0);
+       if (err)
+               return err;
+@@ -2557,7 +2567,7 @@ static int airoha_gpio_set_direction(str
+       index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
+ 
+       return regmap_update_bits(pinctrl->regmap,
+-                                pinctrl->gpiochip.dir[index], mask,
++                                pinctrl->gpio_regs->dir[index], mask,
+                                 !input ? mask : 0);
+ }
+ 
+@@ -2584,7 +2594,7 @@ static void airoha_irq_unmask(struct irq
+ {
+       struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+       struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+-      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
++      struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs;
+       u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+@@ -2599,18 +2609,18 @@ static void airoha_irq_unmask(struct irq
+               val = val << 1;
+               fallthrough;
+       case IRQ_TYPE_LEVEL_HIGH:
+-              regmap_update_bits(pinctrl->regmap, gpiochip->level[index],
++              regmap_update_bits(pinctrl->regmap, gpio_regs->level[index],
+                                  mask, val);
+               break;
+       case IRQ_TYPE_EDGE_FALLING:
+               val = val << 1;
+               fallthrough;
+       case IRQ_TYPE_EDGE_RISING:
+-              regmap_update_bits(pinctrl->regmap, gpiochip->edge[index],
++              regmap_update_bits(pinctrl->regmap, gpio_regs->edge[index],
+                                  mask, val);
+               break;
+       case IRQ_TYPE_EDGE_BOTH:
+-              regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask);
++              regmap_set_bits(pinctrl->regmap, gpio_regs->edge[index], mask);
+               break;
+       default:
+               break;
+@@ -2621,7 +2631,7 @@ static void airoha_irq_mask(struct irq_d
+ {
+       struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+       struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+-      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
++      struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs;
+       u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       u32 mask = GENMASK(2 * offset + 1, 2 * offset);
+@@ -2629,8 +2639,8 @@ static void airoha_irq_mask(struct irq_d
+       if (data->hwirq >= AIROHA_NUM_PINS)
+               return;
+ 
+-      regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask);
+-      regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask);
++      regmap_clear_bits(pinctrl->regmap, gpio_regs->level[index], mask);
++      regmap_clear_bits(pinctrl->regmap, gpio_regs->edge[index], mask);
+       gpiochip_disable_irq(gc, irqd_to_hwirq(data));
+ }
+ 
+@@ -2638,14 +2648,14 @@ static void airoha_irq_ack(struct irq_da
+ {
+       struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
+       struct airoha_pinctrl *pinctrl = gpiochip_get_data(gc);
+-      struct airoha_pinctrl_gpiochip *gpiochip = &pinctrl->gpiochip;
++      struct airoha_gpiochip_regs *gpio_regs = pinctrl->gpio_regs;
+       u8 offset = data->hwirq % AIROHA_PIN_BANK_SIZE;
+       u8 index = data->hwirq / AIROHA_PIN_BANK_SIZE;
+ 
+       if (data->hwirq >= AIROHA_NUM_PINS)
+               return;
+ 
+-      regmap_write(pinctrl->regmap, gpiochip->status[index], BIT(offset));
++      regmap_write(pinctrl->regmap, gpio_regs->status[index], BIT(offset));
+ }
+ 
+ static int airoha_irq_type(struct irq_data *data, unsigned int type)
+@@ -2683,12 +2693,12 @@ static irqreturn_t airoha_irq_handler(in
+       int i;
+ 
+       for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) {
+-              struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq;
++              struct gpio_irq_chip *girq = &pinctrl->gpiochip.irq;
+               u32 regmap;
+               unsigned long status;
+               int irq;
+ 
+-              if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i],
++              if (regmap_read(pinctrl->regmap, pinctrl->gpio_regs->status[i],
+                               &regmap))
+                       continue;
+ 
+@@ -2698,7 +2708,7 @@ static irqreturn_t airoha_irq_handler(in
+ 
+                       generic_handle_domain_irq(girq->domain, offset);
+                       regmap_write(pinctrl->regmap,
+-                                   pinctrl->gpiochip.status[i], BIT(irq));
++                                   pinctrl->gpio_regs->status[i], BIT(irq));
+               }
+               handled |= !!status;
+       }
+@@ -2719,8 +2729,7 @@ static const struct irq_chip airoha_gpio
+ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
+                                       struct platform_device *pdev)
+ {
+-      struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip;
+-      struct gpio_chip *gc = &chip->chip;
++      struct gpio_chip *gc = &pinctrl->gpiochip;
+       struct gpio_irq_chip *girq = &gc->irq;
+       struct device *dev = &pdev->dev;
+       int irq, err;
+@@ -2820,7 +2829,7 @@ static int airoha_pinmux_set_direction(s
+       if (pin < 0)
+               return pin;
+ 
+-      return airoha_gpio_set_direction(&pinctrl->gpiochip.chip, pin, input);
++      return airoha_gpio_set_direction(&pinctrl->gpiochip, pin, input);
+ }
+ 
+ static const struct pinmux_ops airoha_pmxops = {
+@@ -2933,7 +2942,7 @@ static int airoha_pinconf_get_direction(
+       if (pin < 0)
+               return pin;
+ 
+-      ret = airoha_gpio_get_direction(&pinctrl->gpiochip.chip, pin);
++      ret = airoha_gpio_get_direction(&pinctrl->gpiochip, pin);
+       if (ret < 0)
+               return ret;
+ 
+@@ -3011,7 +3020,7 @@ static int airoha_pinconf_set_pin_value(
+       if (pin < 0)
+               return pin;
+ 
+-      return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value);
++      return airoha_gpio_set(&pinctrl->gpiochip, pin, value);
+ }
+ 
+ static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev,
+@@ -3214,16 +3223,7 @@ static int airoha_pinctrl_probe(struct p
+       pinctrl->desc.pins = data->pins;
+       pinctrl->desc.npins = data->num_pins;
+ 
+-      /*
+-       * some pinctrl operations (ex: get_direction) might use gpio registers
+-       * before gpio chip abstraction will be completely initialized.
+-       */
+-      pinctrl->gpiochip.data = gpio_data_regs;
+-      pinctrl->gpiochip.dir = gpio_dir_regs;
+-      pinctrl->gpiochip.out = gpio_out_regs;
+-      pinctrl->gpiochip.status = irq_status_regs;
+-      pinctrl->gpiochip.level = irq_level_regs;
+-      pinctrl->gpiochip.edge = irq_edge_regs;
++      pinctrl->gpio_regs = &airoha_gpiochip_regs;
+ 
+       err = devm_pinctrl_register_and_init(dev, &pinctrl->desc,
+                                            pinctrl, &pinctrl->ctrl);

diff --git a/target/linux/airoha/patches-6.18/202-19-v7.3-pinctrl-airoha-move-common-definitions-to-the-se.patch b/target/linux/airoha/patches-6.18/202-19-v7.3-pinctrl-airoha-move-common-definitions-to-the-se.patch
new file mode 100644 (file)
index 0000000..78281c6
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-19-v7.3-pinctrl-airoha-move-common-definitions-to-the-se.patch
@@ -0,0 +1,647 @@
+From 7a0405d44274cda1eb348a820f9ac9174c300019 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Thu, 4 Jun 2026 05:14:15 +0300
+Subject: [PATCH v11 24/37] pinctrl: airoha: move common definitions to the
+ separate header
+
+Let's move the SoC independent definitions and declarations of structures
+required for Airoha SoC-specific pinctrl drivers to a common header. Later
+we'll have several SoC-specific drivers, so this step is necessary.
+
+We will not move to the common header file other register addresses,
+register bitfields definitions and macroses that use SoC specific
+information. We will keep SoC specific definitions inside SoC specific
+files.
+
+No functional changes.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/airoha-common.h  | 142 ++++++++
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 411 ++++++++----------------
+ 2 files changed, 283 insertions(+), 270 deletions(-)
+ create mode 100644 drivers/pinctrl/airoha/airoha-common.h
+
+--- /dev/null
++++ b/drivers/pinctrl/airoha/airoha-common.h
+@@ -0,0 +1,142 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
++ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
++ * Author: Markus Gothe <markus.gothe@genexis.eu>
++ */
++
++#ifndef __AIROHA_COMMON_HEADER__
++#define __AIROHA_COMMON_HEADER__
++
++#include <dt-bindings/pinctrl/mt65xx.h>
++#include <linux/bitfield.h>
++#include <linux/bits.h>
++#include <linux/cleanup.h>
++#include <linux/gpio/driver.h>
++#include <linux/interrupt.h>
++#include <linux/io.h>
++#include <linux/irq.h>
++#include <linux/irqdomain.h>
++#include <linux/mfd/syscon.h>
++#include <linux/of.h>
++#include <linux/of_irq.h>
++#include <linux/of_platform.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/pinconf-generic.h>
++#include <linux/pinctrl/pinmux.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/types.h>
++
++#include "../core.h"
++#include "../pinconf.h"
++#include "../pinmux.h"
++
++#define AIROHA_NUM_PINS                               64
++#define AIROHA_PIN_BANK_SIZE                  (AIROHA_NUM_PINS / 2)
++#define AIROHA_REG_GPIOCTRL_NUM_PIN           (AIROHA_NUM_PINS / 4)
++
++#define PINCTRL_PIN_GROUP(id, table)                                  \
++      PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
++
++#define PINCTRL_FUNC_DESC(id, table)                                  \
++      {                                                               \
++              .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
++                                          ARRAY_SIZE(table##_groups)),\
++              .groups = table##_func_group,                           \
++              .group_size = ARRAY_SIZE(table##_func_group),           \
++      }
++
++#define PINCTRL_CONF_DESC(p, offset, mask)                            \
++      {                                                               \
++              .pin = p,                                               \
++              .reg = { offset, mask },                                \
++      }
++
++struct airoha_pinctrl_reg {
++      u32 offset;
++      u32 mask;
++};
++
++enum airoha_pinctrl_mux_func {
++      AIROHA_FUNC_MUX,
++      AIROHA_FUNC_PWM_MUX,
++      AIROHA_FUNC_PWM_EXT_MUX,
++};
++
++struct airoha_pinctrl_func_group {
++      const char *name;
++      struct {
++              enum airoha_pinctrl_mux_func mux;
++              u32 offset;
++              u32 mask;
++              u32 val;
++      } regmap[2];
++      int regmap_size;
++};
++
++struct airoha_pinctrl_func {
++      const struct pinfunction desc;
++      const struct airoha_pinctrl_func_group *groups;
++      u8 group_size;
++};
++
++struct airoha_pinctrl_conf {
++      u32 pin;
++      struct airoha_pinctrl_reg reg;
++};
++
++struct airoha_gpiochip_regs {
++      /* gpio */
++      const u32 *data;
++      const u32 *dir;
++      const u32 *out;
++      /* irq */
++      const u32 *status;
++      const u32 *level;
++      const u32 *edge;
++};
++
++struct airoha_pinctrl_confs_info {
++      const struct airoha_pinctrl_conf *confs;
++      unsigned int num_confs;
++};
++
++enum airoha_pinctrl_confs_type {
++      AIROHA_PINCTRL_CONFS_PULLUP,
++      AIROHA_PINCTRL_CONFS_PULLDOWN,
++      AIROHA_PINCTRL_CONFS_DRIVE_E2,
++      AIROHA_PINCTRL_CONFS_DRIVE_E4,
++      AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
++
++      AIROHA_PINCTRL_CONFS_MAX,
++};
++
++struct airoha_pinctrl {
++      struct pinctrl_dev *ctrl;
++
++      struct pinctrl_desc desc;
++      const struct pingroup *grps;
++      const struct airoha_pinctrl_func *funcs;
++      const struct airoha_pinctrl_confs_info *confs_info;
++
++      struct regmap *chip_scu;
++      struct regmap *regmap;
++
++      struct gpio_chip gpiochip;
++      struct airoha_gpiochip_regs *gpio_regs;
++};
++
++struct airoha_pinctrl_match_data {
++      const struct pinctrl_pin_desc *pins;
++      const unsigned int num_pins;
++      const struct pingroup *grps;
++      const unsigned int num_grps;
++      const struct airoha_pinctrl_func *funcs;
++      const unsigned int num_funcs;
++      const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
++};
++
++#endif
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -5,47 +5,7 @@
+  * Author: Markus Gothe <markus.gothe@genexis.eu>
+  */
+ 
+-#include <dt-bindings/pinctrl/mt65xx.h>
+-#include <linux/bitfield.h>
+-#include <linux/bits.h>
+-#include <linux/cleanup.h>
+-#include <linux/gpio/driver.h>
+-#include <linux/interrupt.h>
+-#include <linux/io.h>
+-#include <linux/irq.h>
+-#include <linux/irqdomain.h>
+-#include <linux/mfd/syscon.h>
+-#include <linux/of.h>
+-#include <linux/of_irq.h>
+-#include <linux/of_platform.h>
+-#include <linux/pinctrl/consumer.h>
+-#include <linux/pinctrl/pinctrl.h>
+-#include <linux/pinctrl/pinconf.h>
+-#include <linux/pinctrl/pinconf-generic.h>
+-#include <linux/pinctrl/pinmux.h>
+-#include <linux/platform_device.h>
+-#include <linux/regmap.h>
+-
+-#include "../core.h"
+-#include "../pinconf.h"
+-#include "../pinmux.h"
+-
+-#define PINCTRL_PIN_GROUP(id, table)                                  \
+-      PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins))
+-
+-#define PINCTRL_FUNC_DESC(id, table)                                  \
+-      {                                                               \
+-              .desc = PINCTRL_PINFUNCTION(id, table##_groups, \
+-                                          ARRAY_SIZE(table##_groups)),\
+-              .groups = table##_func_group,                           \
+-              .group_size = ARRAY_SIZE(table##_func_group),           \
+-      }
+-
+-#define PINCTRL_CONF_DESC(p, offset, mask)                            \
+-      {                                                               \
+-              .pin = p,                                               \
+-              .reg = { offset, mask },                                \
+-      }
++#include "airoha-common.h"
+ 
+ /* MUX */
+ #define REG_GPIO_2ND_I2C_MODE                 0x0214
+@@ -231,6 +191,8 @@
+ #define REG_GPIO_INT_LEVEL                    0x0010
+ #define REG_GPIO_OE                           0x0014
+ #define REG_GPIO_CTRL1                                0x0020
++#define REG_GPIO_CTRL2                                0x0060
++#define REG_GPIO_CTRL3                                0x0064
+ 
+ /* PWM MODE CONF */
+ #define REG_GPIO_FLASH_MODE_CFG                       0x0034
+@@ -251,9 +213,6 @@
+ #define GPIO1_FLASH_MODE_CFG                  BIT(1)
+ #define GPIO0_FLASH_MODE_CFG                  BIT(0)
+ 
+-#define REG_GPIO_CTRL2                                0x0060
+-#define REG_GPIO_CTRL3                                0x0064
+-
+ /* PWM MODE CONF EXT */
+ #define REG_GPIO_FLASH_MODE_CFG_EXT           0x0068
+ #define GPIO51_FLASH_MODE_CFG                 BIT(31)
+@@ -299,20 +258,145 @@
+ #define REG_GPIO_INT_LEVEL2                   0x0090
+ #define REG_GPIO_INT_LEVEL3                   0x0094
+ 
+-#define AIROHA_NUM_PINS                               64
+-#define AIROHA_PIN_BANK_SIZE                  (AIROHA_NUM_PINS / 2)
+-#define AIROHA_REG_GPIOCTRL_NUM_PIN           (AIROHA_NUM_PINS / 4)
+-
+-struct airoha_gpiochip_regs {
+-      /* gpio */
+-      const u32 *data;
+-      const u32 *dir;
+-      const u32 *out;
+-      /* irq */
+-      const u32 *status;
+-      const u32 *level;
+-      const u32 *edge;
+-};
++#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      0                                       \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++/* PWM */
++#define AIROHA_PINCTRL_PWM(gpio, mux_val)             \
++      {                                               \
++              .name = (gpio),                         \
++              .regmap[0] = {                          \
++                      AIROHA_FUNC_PWM_MUX,            \
++                      REG_GPIO_FLASH_MODE_CFG,        \
++                      (mux_val),                      \
++                      (mux_val)                       \
++              },                                      \
++              .regmap_size = 1,                       \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)         \
++      {                                               \
++              .name = (gpio),                         \
++              .regmap[0] = {                          \
++                      AIROHA_FUNC_PWM_EXT_MUX,        \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,    \
++                      (mux_val),                      \
++                      (mux_val)                       \
++              },                                      \
++              .regmap_size = 1,                       \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED0_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED1_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)                     \
++      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,         \
++                              (pin), (val))
++#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,       \
++                              (pin), (val))
++#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,       \
++                              (pin), (val))
++#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,       \
++                              (pin), (val))
++#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)                        \
++      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,    \
++                              (pin), (val))
++#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)                     \
++      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,         \
++                              (pin), (val))
++#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,       \
++                              (pin), (val))
++#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,       \
++                              (pin), (val))
++#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)                   \
++      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,       \
++                              (pin), (val))
++#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)                        \
++      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,    \
++                              (pin), (val))
+ 
+ static const u32 gpio_data_regs[] = {
+       REG_GPIO_DATA,
+@@ -359,79 +443,6 @@ static struct airoha_gpiochip_regs airoh
+       .edge = irq_edge_regs,
+ };
+ 
+-struct airoha_pinctrl_reg {
+-      u32 offset;
+-      u32 mask;
+-};
+-
+-enum airoha_pinctrl_mux_func {
+-      AIROHA_FUNC_MUX,
+-      AIROHA_FUNC_PWM_MUX,
+-      AIROHA_FUNC_PWM_EXT_MUX,
+-};
+-
+-struct airoha_pinctrl_func_group {
+-      const char *name;
+-      struct {
+-              enum airoha_pinctrl_mux_func mux;
+-              u32 offset;
+-              u32 mask;
+-              u32 val;
+-      } regmap[2];
+-      int regmap_size;
+-};
+-
+-struct airoha_pinctrl_func {
+-      const struct pinfunction desc;
+-      const struct airoha_pinctrl_func_group *groups;
+-      u8 group_size;
+-};
+-
+-struct airoha_pinctrl_conf {
+-      u32 pin;
+-      struct airoha_pinctrl_reg reg;
+-};
+-
+-struct airoha_pinctrl_confs_info {
+-      const struct airoha_pinctrl_conf *confs;
+-      unsigned int num_confs;
+-};
+-
+-enum airoha_pinctrl_confs_type {
+-      AIROHA_PINCTRL_CONFS_PULLUP,
+-      AIROHA_PINCTRL_CONFS_PULLDOWN,
+-      AIROHA_PINCTRL_CONFS_DRIVE_E2,
+-      AIROHA_PINCTRL_CONFS_DRIVE_E4,
+-      AIROHA_PINCTRL_CONFS_PCIE_RST_OD,
+-
+-      AIROHA_PINCTRL_CONFS_MAX,
+-};
+-
+-struct airoha_pinctrl {
+-      struct pinctrl_dev *ctrl;
+-
+-      struct pinctrl_desc desc;
+-      const struct pingroup *grps;
+-      const struct airoha_pinctrl_func *funcs;
+-      const struct airoha_pinctrl_confs_info *confs_info;
+-
+-      struct regmap *chip_scu;
+-      struct regmap *regmap;
+-
+-      struct gpio_chip gpiochip;
+-      struct airoha_gpiochip_regs *gpio_regs;
+-};
+-
+-struct airoha_pinctrl_match_data {
+-      const struct pinctrl_pin_desc *pins;
+-      const unsigned int num_pins;
+-      const struct pingroup *grps;
+-      const unsigned int num_grps;
+-      const struct airoha_pinctrl_func *funcs;
+-      const unsigned int num_funcs;
+-      const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+-};
+-
+ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+       PINCTRL_PIN(0, "uart1_txd"),
+       PINCTRL_PIN(1, "uart1_rxd"),
+@@ -1465,36 +1476,6 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (mux_val),                              \
+-                      (mux_val)                               \
+-              },                                              \
+-              .regmap_size = 1,                               \
+-      }
+-
+-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_PWM_EXT_MUX,                \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
+-                      (mux_val),                              \
+-                      0                                       \
+-              },                                              \
+-              .regmap[1] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (smux_val),                             \
+-                      (smux_val)                              \
+-              },                                              \
+-              .regmap_size = 2,                               \
+-      }
+-
+ static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+       AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+                               GPIO_PCIE_RESET0_MASK),
+@@ -1587,49 +1568,6 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-/* PWM */
+-#define AIROHA_PINCTRL_PWM(gpio, mux_val)             \
+-      {                                               \
+-              .name = (gpio),                         \
+-              .regmap[0] = {                          \
+-                      AIROHA_FUNC_PWM_MUX,            \
+-                      REG_GPIO_FLASH_MODE_CFG,        \
+-                      (mux_val),                      \
+-                      (mux_val)                       \
+-              },                                      \
+-              .regmap_size = 1,                       \
+-      }                                               \
+-
+-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)         \
+-      {                                               \
+-              .name = (gpio),                         \
+-              .regmap[0] = {                          \
+-                      AIROHA_FUNC_PWM_EXT_MUX,        \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,    \
+-                      (mux_val),                      \
+-                      (mux_val)                       \
+-              },                                      \
+-              .regmap_size = 1,                       \
+-      }                                               \
+-
+-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_PWM_EXT_MUX,                \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
+-                      (mux_val),                              \
+-                      (mux_val)                               \
+-              },                                              \
+-              .regmap[1] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (smux_val),                             \
+-                      (smux_val)                              \
+-              },                                              \
+-              .regmap_size = 2,                               \
+-      }
+-
+ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+       AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+@@ -1746,42 +1684,6 @@ static const struct airoha_pinctrl_func_
+                                  AN7583_MDC_0_GPIO_MODE_MASK),
+ };
+ 
+-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
+-      {                                                               \
+-              .name = (gpio),                                         \
+-              .regmap[0] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
+-                      (mux_val),                                      \
+-                      (mux_val),                                      \
+-              },                                                      \
+-              .regmap[1] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_LAN_LED0_MAPPING,                           \
+-                      (map_mask),                                     \
+-                      (map_val),                                      \
+-              },                                                      \
+-              .regmap_size = 2,                                       \
+-      }
+-
+-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
+-      {                                                               \
+-              .name = (gpio),                                         \
+-              .regmap[0] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
+-                      (mux_val),                                      \
+-                      (mux_val),                                      \
+-              },                                                      \
+-              .regmap[1] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_LAN_LED1_MAPPING,                           \
+-                      (map_mask),                                     \
+-                      (map_val),                                      \
+-              },                                                      \
+-              .regmap_size = 2,                                       \
+-      }
+-
+ static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+@@ -2902,37 +2804,6 @@ static int airoha_pinctrl_set_conf(struc
+       return 0;
+ }
+ 
+-#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)                     \
+-      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,         \
+-                              (pin), (val))
+-#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val)                        \
+-      airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,    \
+-                              (pin), (val))
+-#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val)                     \
+-      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,         \
+-                              (pin), (val))
+-#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val)                   \
+-      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4,       \
+-                              (pin), (val))
+-#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val)                        \
+-      airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD,    \
+-                              (pin), (val))
+-
+ static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p)
+ {
+       struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);

diff --git a/target/linux/airoha/patches-6.18/202-20-v7.3-pinctrl-airoha-split-driver-on-shared-code-and-S.patch b/target/linux/airoha/patches-6.18/202-20-v7.3-pinctrl-airoha-split-driver-on-shared-code-and-S.patch
new file mode 100644 (file)
index 0000000..f875b0c
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-20-v7.3-pinctrl-airoha-split-driver-on-shared-code-and-S.patch
@@ -0,0 +1,5503 @@
+From 47cc3851c61b8f89b18860cc5b7863c0a66b8d19 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Thu, 4 Jun 2026 06:13:54 +0300
+Subject: [PATCH v11 25/37] pinctrl: airoha: split driver on shared code and
+ SoC specific drivers
+
+Split combined an7581/an7583 source file on a
+ * shared pinctrl code (pinctrl-airoha.c)
+ * an7581 specific pinctrl driver (pinctrl-an7581.c)
+ * an7583 specific pinctrl driver (pinctrl-an7583.c)
+
+Ininialization code was adapted a bit to work properly for shared
+and SoC specific cases.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/Kconfig          |   24 +-
+ drivers/pinctrl/airoha/Makefile         |    5 +
+ drivers/pinctrl/airoha/airoha-common.h  |    4 +
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 2378 +----------------------
+ drivers/pinctrl/airoha/pinctrl-an7581.c | 1486 ++++++++++++++
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 1476 ++++++++++++++
+ 6 files changed, 2999 insertions(+), 2374 deletions(-)
+ create mode 100644 drivers/pinctrl/airoha/pinctrl-an7581.c
+ create mode 100644 drivers/pinctrl/airoha/pinctrl-an7583.c
+
+--- a/drivers/pinctrl/airoha/Kconfig
++++ b/drivers/pinctrl/airoha/Kconfig
+@@ -3,9 +3,9 @@ menu "Airoha pinctrl drivers"
+       depends on ARCH_AIROHA || COMPILE_TEST
+ 
+ config PINCTRL_AIROHA
+-      tristate "Airoha EN7581 pin control"
++      tristate "Airoha pin control"
+       depends on OF
+-      depends on ARM64 || COMPILE_TEST
++      depends on ARCH_AIROHA || COMPILE_TEST
+       select PINMUX
+       select GENERIC_PINCONF
+       select GENERIC_PINCTRL_GROUPS
+@@ -13,8 +13,26 @@ config PINCTRL_AIROHA
+       select GPIOLIB
+       select GPIOLIB_IRQCHIP
+       select REGMAP_MMIO
++      imply PINCTRL_AIROHA_AN7581
++      imply PINCTRL_AIROHA_AN7583
++      help
++        Shared pin controller and gpio driver code for different
++        Airoha SoCs.
++
++config PINCTRL_AIROHA_AN7581
++      tristate "AN7581 pinctrl"
++      depends on ARM64 || COMPILE_TEST
++      depends on PINCTRL_AIROHA
++      help
++        Say yes here to support pin controller and gpio driver
++        on Airoha AN7581, AN7566, AN7551 and other compatible SoCs.
++
++config PINCTRL_AIROHA_AN7583
++      tristate "AN7583 pinctrl"
++      depends on ARM64 || COMPILE_TEST
++      depends on PINCTRL_AIROHA
+       help
+         Say yes here to support pin controller and gpio driver
+-        on Airoha EN7581 SoC.
++        on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
+ 
+ endmenu
+--- a/drivers/pinctrl/airoha/Makefile
++++ b/drivers/pinctrl/airoha/Makefile
+@@ -1,3 +1,8 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
++# shared code
+ obj-$(CONFIG_PINCTRL_AIROHA)          += pinctrl-airoha.o
++
++# SoC drivers
++obj-$(CONFIG_PINCTRL_AIROHA_AN7581)   += pinctrl-an7581.o
++obj-$(CONFIG_PINCTRL_AIROHA_AN7583)   += pinctrl-an7583.o
+--- a/drivers/pinctrl/airoha/airoha-common.h
++++ b/drivers/pinctrl/airoha/airoha-common.h
+@@ -130,6 +130,8 @@ struct airoha_pinctrl {
+ };
+ 
+ struct airoha_pinctrl_match_data {
++      const char *pinctrl_name;
++      struct module *pinctrl_owner;
+       const struct pinctrl_pin_desc *pins;
+       const unsigned int num_pins;
+       const struct pingroup *grps;
+@@ -139,4 +141,6 @@ struct airoha_pinctrl_match_data {
+       const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
+ };
+ 
++int airoha_pinctrl_probe(struct platform_device *pdev);
++
+ #endif
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -7,182 +7,6 @@
+ 
+ #include "airoha-common.h"
+ 
+-/* MUX */
+-#define REG_GPIO_2ND_I2C_MODE                 0x0214
+-#define GPIO_MDC_IO_MASTER_MODE_MASK          BIT(14)
+-#define GPIO_I2C_MASTER_MODE_MODE             BIT(13)
+-#define GPIO_I2S_MODE_MASK                    BIT(12)
+-#define GPIO_I2C_SLAVE_MODE_MODE              BIT(11)
+-#define GPIO_LAN3_LED1_MODE_MASK              BIT(10)
+-#define GPIO_LAN3_LED0_MODE_MASK              BIT(9)
+-#define GPIO_LAN2_LED1_MODE_MASK              BIT(8)
+-#define GPIO_LAN2_LED0_MODE_MASK              BIT(7)
+-#define GPIO_LAN1_LED1_MODE_MASK              BIT(6)
+-#define GPIO_LAN1_LED0_MODE_MASK              BIT(5)
+-#define GPIO_LAN0_LED1_MODE_MASK              BIT(4)
+-#define GPIO_LAN0_LED0_MODE_MASK              BIT(3)
+-#define PON_TOD_1PPS_MODE_MASK                        BIT(2)
+-#define GSW_TOD_1PPS_MODE_MASK                        BIT(1)
+-#define GPIO_2ND_I2C_MODE_MASK                        BIT(0)
+-
+-#define REG_GPIO_SPI_CS1_MODE                 0x0218
+-#define AN7583_GPIO_MDC_IO_MASTER_MODE_MASK   BIT(22)
+-#define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
+-#define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
+-#define GPIO_PCM_SPI_CS2_MODE_P156_MASK               BIT(19)
+-#define GPIO_PCM_SPI_CS2_MODE_P128_MASK               BIT(18)
+-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK     BIT(18)
+-#define GPIO_PCM_SPI_CS1_MODE_MASK            BIT(17)
+-#define GPIO_PCM_SPI_MODE_MASK                        BIT(16)
+-#define GPIO_PCM2_MODE_MASK                   BIT(13)
+-#define GPIO_PCM1_MODE_MASK                   BIT(12)
+-#define GPIO_PCM_INT_MODE_MASK                        BIT(9)
+-#define GPIO_PCM_RESET_MODE_MASK              BIT(8)
+-#define GPIO_SPI_QUAD_MODE_MASK                       BIT(4)
+-#define GPIO_SPI_CS4_MODE_MASK                        BIT(3)
+-#define GPIO_SPI_CS3_MODE_MASK                        BIT(2)
+-#define GPIO_SPI_CS2_MODE_MASK                        BIT(1)
+-#define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
+-
+-#define REG_GPIO_PON_MODE                     0x021c
+-#define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
+-#define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
+-#define AN7583_UART_RXD_GPIO_MODE_MASK                BIT(24)
+-#define AN7583_UART_TXD_GPIO_MODE_MASK                BIT(23)
+-#define AN7583_SPI_MISO_GPIO_MODE_MASK                BIT(22)
+-#define AN7583_SPI_MOSI_GPIO_MODE_MASK                BIT(21)
+-#define AN7583_SPI_CS_GPIO_MODE_MASK          BIT(20)
+-#define AN7583_SPI_CLK_GPIO_MODE_MASK         BIT(19)
+-#define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
+-#define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
+-#define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
+-#define AN7583_I2C0_SCL_GPIO_MODE_MASK                BIT(15)
+-#define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
+-#define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
+-#define GPIO_PCIE_RESET2_MASK                 BIT(12)
+-#define SIPO_RCLK_MODE_MASK                   BIT(11)
+-#define GPIO_PCIE_RESET1_MASK                 BIT(10)
+-#define GPIO_PCIE_RESET0_MASK                 BIT(9)
+-#define GPIO_UART5_MODE_MASK                  BIT(8)
+-#define GPIO_UART4_MODE_MASK                  BIT(7)
+-#define GPIO_HSUART_CTS_RTS_MODE_MASK         BIT(6)
+-#define GPIO_HSUART_MODE_MASK                 BIT(5)
+-#define GPIO_UART2_CTS_RTS_MODE_MASK          BIT(4)
+-#define GPIO_UART2_MODE_MASK                  BIT(3)
+-#define GPIO_SIPO_MODE_MASK                   BIT(2)
+-#define GPIO_EMMC_MODE_MASK                   BIT(1)
+-#define GPIO_PON_MODE_MASK                    BIT(0)
+-
+-#define REG_NPU_UART_EN                               0x0224
+-#define JTAG_UDI_EN_MASK                      BIT(4)
+-#define JTAG_DFD_EN_MASK                      BIT(3)
+-
+-#define REG_FORCE_GPIO_EN                     0x0228
+-#define FORCE_GPIO_EN(n)                      BIT(n)
+-
+-/* LED MAP */
+-#define REG_LAN_LED0_MAPPING                  0x027c
+-#define REG_LAN_LED1_MAPPING                  0x0280
+-
+-#define LAN4_LED_MAPPING_MASK                 GENMASK(18, 16)
+-#define LAN4_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
+-
+-#define LAN3_LED_MAPPING_MASK                 GENMASK(14, 12)
+-#define LAN3_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
+-
+-#define LAN2_LED_MAPPING_MASK                 GENMASK(10, 8)
+-#define LAN2_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
+-
+-#define LAN1_LED_MAPPING_MASK                 GENMASK(6, 4)
+-#define LAN1_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
+-
+-#define LAN0_LED_MAPPING_MASK                 GENMASK(2, 0)
+-#define LAN0_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
+-
+-/* CONF */
+-#define REG_I2C_SDA_E2                                0x001c
+-#define AN7583_I2C1_SCL_E2_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_E2_MASK                       BIT(15)
+-#define SPI_MISO_E2_MASK                      BIT(14)
+-#define SPI_MOSI_E2_MASK                      BIT(13)
+-#define SPI_CLK_E2_MASK                               BIT(12)
+-#define SPI_CS0_E2_MASK                               BIT(11)
+-#define PCIE2_RESET_E2_MASK                   BIT(10)
+-#define PCIE1_RESET_E2_MASK                   BIT(9)
+-#define PCIE0_RESET_E2_MASK                   BIT(8)
+-#define AN7583_MDIO_0_E2_MASK                 BIT(5)
+-#define AN7583_MDC_0_E2_MASK                  BIT(4)
+-#define UART1_RXD_E2_MASK                     BIT(3)
+-#define UART1_TXD_E2_MASK                     BIT(2)
+-#define I2C_SCL_E2_MASK                               BIT(1)
+-#define I2C_SDA_E2_MASK                               BIT(0)
+-
+-#define REG_I2C_SDA_E4                                0x0020
+-#define AN7583_I2C1_SCL_E4_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_E4_MASK                       BIT(15)
+-#define SPI_MISO_E4_MASK                      BIT(14)
+-#define SPI_MOSI_E4_MASK                      BIT(13)
+-#define SPI_CLK_E4_MASK                               BIT(12)
+-#define SPI_CS0_E4_MASK                               BIT(11)
+-#define PCIE2_RESET_E4_MASK                   BIT(10)
+-#define PCIE1_RESET_E4_MASK                   BIT(9)
+-#define PCIE0_RESET_E4_MASK                   BIT(8)
+-#define AN7583_MDIO_0_E4_MASK                 BIT(5)
+-#define AN7583_MDC_0_E4_MASK                  BIT(4)
+-#define UART1_RXD_E4_MASK                     BIT(3)
+-#define UART1_TXD_E4_MASK                     BIT(2)
+-#define I2C_SCL_E4_MASK                               BIT(1)
+-#define I2C_SDA_E4_MASK                               BIT(0)
+-
+-#define REG_GPIO_L_E2                         0x0024
+-#define REG_GPIO_L_E4                         0x0028
+-#define REG_GPIO_H_E2                         0x002c
+-#define REG_GPIO_H_E4                         0x0030
+-
+-#define REG_I2C_SDA_PU                                0x0044
+-#define AN7583_I2C1_SCL_PU_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_PU_MASK                       BIT(15)
+-#define SPI_MISO_PU_MASK                      BIT(14)
+-#define SPI_MOSI_PU_MASK                      BIT(13)
+-#define SPI_CLK_PU_MASK                               BIT(12)
+-#define SPI_CS0_PU_MASK                               BIT(11)
+-#define PCIE2_RESET_PU_MASK                   BIT(10)
+-#define PCIE1_RESET_PU_MASK                   BIT(9)
+-#define PCIE0_RESET_PU_MASK                   BIT(8)
+-#define AN7583_MDIO_0_PU_MASK                 BIT(5)
+-#define AN7583_MDC_0_PU_MASK                  BIT(4)
+-#define UART1_RXD_PU_MASK                     BIT(3)
+-#define UART1_TXD_PU_MASK                     BIT(2)
+-#define I2C_SCL_PU_MASK                               BIT(1)
+-#define I2C_SDA_PU_MASK                               BIT(0)
+-
+-#define REG_I2C_SDA_PD                                0x0048
+-#define AN7583_I2C1_SCL_PD_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_PD_MASK                       BIT(15)
+-#define SPI_MISO_PD_MASK                      BIT(14)
+-#define SPI_MOSI_PD_MASK                      BIT(13)
+-#define SPI_CLK_PD_MASK                               BIT(12)
+-#define SPI_CS0_PD_MASK                               BIT(11)
+-#define PCIE2_RESET_PD_MASK                   BIT(10)
+-#define PCIE1_RESET_PD_MASK                   BIT(9)
+-#define PCIE0_RESET_PD_MASK                   BIT(8)
+-#define AN7583_MDIO_0_PD_MASK                 BIT(5)
+-#define AN7583_MDC_0_PD_MASK                  BIT(4)
+-#define UART1_RXD_PD_MASK                     BIT(3)
+-#define UART1_TXD_PD_MASK                     BIT(2)
+-#define I2C_SCL_PD_MASK                               BIT(1)
+-#define I2C_SDA_PD_MASK                               BIT(0)
+-
+-#define REG_GPIO_L_PU                         0x004c
+-#define REG_GPIO_L_PD                         0x0050
+-#define REG_GPIO_H_PU                         0x0054
+-#define REG_GPIO_H_PD                         0x0058
+-
+-#define REG_PCIE_RESET_OD                     0x018c
+-#define PCIE2_RESET_OD_MASK                   BIT(2)
+-#define PCIE1_RESET_OD_MASK                   BIT(1)
+-#define PCIE0_RESET_OD_MASK                   BIT(0)
+-
+ /* GPIOs */
+ #define REG_GPIO_CTRL                         0x0000
+ #define REG_GPIO_DATA                         0x0004
+@@ -193,61 +17,6 @@
+ #define REG_GPIO_CTRL1                                0x0020
+ #define REG_GPIO_CTRL2                                0x0060
+ #define REG_GPIO_CTRL3                                0x0064
+-
+-/* PWM MODE CONF */
+-#define REG_GPIO_FLASH_MODE_CFG                       0x0034
+-#define GPIO15_FLASH_MODE_CFG                 BIT(15)
+-#define GPIO14_FLASH_MODE_CFG                 BIT(14)
+-#define GPIO13_FLASH_MODE_CFG                 BIT(13)
+-#define GPIO12_FLASH_MODE_CFG                 BIT(12)
+-#define GPIO11_FLASH_MODE_CFG                 BIT(11)
+-#define GPIO10_FLASH_MODE_CFG                 BIT(10)
+-#define GPIO9_FLASH_MODE_CFG                  BIT(9)
+-#define GPIO8_FLASH_MODE_CFG                  BIT(8)
+-#define GPIO7_FLASH_MODE_CFG                  BIT(7)
+-#define GPIO6_FLASH_MODE_CFG                  BIT(6)
+-#define GPIO5_FLASH_MODE_CFG                  BIT(5)
+-#define GPIO4_FLASH_MODE_CFG                  BIT(4)
+-#define GPIO3_FLASH_MODE_CFG                  BIT(3)
+-#define GPIO2_FLASH_MODE_CFG                  BIT(2)
+-#define GPIO1_FLASH_MODE_CFG                  BIT(1)
+-#define GPIO0_FLASH_MODE_CFG                  BIT(0)
+-
+-/* PWM MODE CONF EXT */
+-#define REG_GPIO_FLASH_MODE_CFG_EXT           0x0068
+-#define GPIO51_FLASH_MODE_CFG                 BIT(31)
+-#define GPIO50_FLASH_MODE_CFG                 BIT(30)
+-#define GPIO49_FLASH_MODE_CFG                 BIT(29)
+-#define GPIO48_FLASH_MODE_CFG                 BIT(28)
+-#define GPIO47_FLASH_MODE_CFG                 BIT(27)
+-#define GPIO46_FLASH_MODE_CFG                 BIT(26)
+-#define GPIO45_FLASH_MODE_CFG                 BIT(25)
+-#define GPIO44_FLASH_MODE_CFG                 BIT(24)
+-#define GPIO43_FLASH_MODE_CFG                 BIT(23)
+-#define GPIO42_FLASH_MODE_CFG                 BIT(22)
+-#define GPIO41_FLASH_MODE_CFG                 BIT(21)
+-#define GPIO40_FLASH_MODE_CFG                 BIT(20)
+-#define GPIO39_FLASH_MODE_CFG                 BIT(19)
+-#define GPIO38_FLASH_MODE_CFG                 BIT(18)
+-#define GPIO37_FLASH_MODE_CFG                 BIT(17)
+-#define GPIO36_FLASH_MODE_CFG                 BIT(16)
+-#define GPIO31_FLASH_MODE_CFG                 BIT(15)
+-#define GPIO30_FLASH_MODE_CFG                 BIT(14)
+-#define GPIO29_FLASH_MODE_CFG                 BIT(13)
+-#define GPIO28_FLASH_MODE_CFG                 BIT(12)
+-#define GPIO27_FLASH_MODE_CFG                 BIT(11)
+-#define GPIO26_FLASH_MODE_CFG                 BIT(10)
+-#define GPIO25_FLASH_MODE_CFG                 BIT(9)
+-#define GPIO24_FLASH_MODE_CFG                 BIT(8)
+-#define GPIO23_FLASH_MODE_CFG                 BIT(7)
+-#define GPIO22_FLASH_MODE_CFG                 BIT(6)
+-#define GPIO21_FLASH_MODE_CFG                 BIT(5)
+-#define GPIO20_FLASH_MODE_CFG                 BIT(4)
+-#define GPIO19_FLASH_MODE_CFG                 BIT(3)
+-#define GPIO18_FLASH_MODE_CFG                 BIT(2)
+-#define GPIO17_FLASH_MODE_CFG                 BIT(1)
+-#define GPIO16_FLASH_MODE_CFG                 BIT(0)
+-
+ #define REG_GPIO_DATA1                                0x0070
+ #define REG_GPIO_OE1                          0x0078
+ #define REG_GPIO_INT1                         0x007c
+@@ -258,115 +27,6 @@
+ #define REG_GPIO_INT_LEVEL2                   0x0090
+ #define REG_GPIO_INT_LEVEL3                   0x0094
+ 
+-#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (mux_val),                              \
+-                      (mux_val)                               \
+-              },                                              \
+-              .regmap_size = 1,                               \
+-      }
+-
+-#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_PWM_EXT_MUX,                \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
+-                      (mux_val),                              \
+-                      0                                       \
+-              },                                              \
+-              .regmap[1] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (smux_val),                             \
+-                      (smux_val)                              \
+-              },                                              \
+-              .regmap_size = 2,                               \
+-      }
+-
+-/* PWM */
+-#define AIROHA_PINCTRL_PWM(gpio, mux_val)             \
+-      {                                               \
+-              .name = (gpio),                         \
+-              .regmap[0] = {                          \
+-                      AIROHA_FUNC_PWM_MUX,            \
+-                      REG_GPIO_FLASH_MODE_CFG,        \
+-                      (mux_val),                      \
+-                      (mux_val)                       \
+-              },                                      \
+-              .regmap_size = 1,                       \
+-      }
+-
+-#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)         \
+-      {                                               \
+-              .name = (gpio),                         \
+-              .regmap[0] = {                          \
+-                      AIROHA_FUNC_PWM_EXT_MUX,        \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,    \
+-                      (mux_val),                      \
+-                      (mux_val)                       \
+-              },                                      \
+-              .regmap_size = 1,                       \
+-      }
+-
+-#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
+-      {                                                       \
+-              .name = (gpio),                                 \
+-              .regmap[0] = {                                  \
+-                      AIROHA_FUNC_PWM_EXT_MUX,                \
+-                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
+-                      (mux_val),                              \
+-                      (mux_val)                               \
+-              },                                              \
+-              .regmap[1] = {                                  \
+-                      AIROHA_FUNC_MUX,                        \
+-                      REG_GPIO_PON_MODE,                      \
+-                      (smux_val),                             \
+-                      (smux_val)                              \
+-              },                                              \
+-              .regmap_size = 2,                               \
+-      }
+-
+-#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
+-      {                                                               \
+-              .name = (gpio),                                         \
+-              .regmap[0] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
+-                      (mux_val),                                      \
+-                      (mux_val),                                      \
+-              },                                                      \
+-              .regmap[1] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_LAN_LED0_MAPPING,                           \
+-                      (map_mask),                                     \
+-                      (map_val),                                      \
+-              },                                                      \
+-              .regmap_size = 2,                                       \
+-      }
+-
+-#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
+-      {                                                               \
+-              .name = (gpio),                                         \
+-              .regmap[0] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
+-                      (mux_val),                                      \
+-                      (mux_val),                                      \
+-              },                                                      \
+-              .regmap[1] = {                                          \
+-                      AIROHA_FUNC_MUX,                                \
+-                      REG_LAN_LED1_MAPPING,                           \
+-                      (map_mask),                                     \
+-                      (map_val),                                      \
+-              },                                                      \
+-              .regmap_size = 2,                                       \
+-      }
+-
+ #define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val)                     \
+       airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP,         \
+                               (pin), (val))
+@@ -443,1955 +103,6 @@ static struct airoha_gpiochip_regs airoh
+       .edge = irq_edge_regs,
+ };
+ 
+-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
+-      PINCTRL_PIN(0, "uart1_txd"),
+-      PINCTRL_PIN(1, "uart1_rxd"),
+-      PINCTRL_PIN(2, "i2c_scl"),
+-      PINCTRL_PIN(3, "i2c_sda"),
+-      PINCTRL_PIN(4, "spi_cs0"),
+-      PINCTRL_PIN(5, "spi_clk"),
+-      PINCTRL_PIN(6, "spi_mosi"),
+-      PINCTRL_PIN(7, "spi_miso"),
+-      PINCTRL_PIN(13, "gpio0"),
+-      PINCTRL_PIN(14, "gpio1"),
+-      PINCTRL_PIN(15, "gpio2"),
+-      PINCTRL_PIN(16, "gpio3"),
+-      PINCTRL_PIN(17, "gpio4"),
+-      PINCTRL_PIN(18, "gpio5"),
+-      PINCTRL_PIN(19, "gpio6"),
+-      PINCTRL_PIN(20, "gpio7"),
+-      PINCTRL_PIN(21, "gpio8"),
+-      PINCTRL_PIN(22, "gpio9"),
+-      PINCTRL_PIN(23, "gpio10"),
+-      PINCTRL_PIN(24, "gpio11"),
+-      PINCTRL_PIN(25, "gpio12"),
+-      PINCTRL_PIN(26, "gpio13"),
+-      PINCTRL_PIN(27, "gpio14"),
+-      PINCTRL_PIN(28, "gpio15"),
+-      PINCTRL_PIN(29, "gpio16"),
+-      PINCTRL_PIN(30, "gpio17"),
+-      PINCTRL_PIN(31, "gpio18"),
+-      PINCTRL_PIN(32, "gpio19"),
+-      PINCTRL_PIN(33, "gpio20"),
+-      PINCTRL_PIN(34, "gpio21"),
+-      PINCTRL_PIN(35, "gpio22"),
+-      PINCTRL_PIN(36, "gpio23"),
+-      PINCTRL_PIN(37, "gpio24"),
+-      PINCTRL_PIN(38, "gpio25"),
+-      PINCTRL_PIN(39, "gpio26"),
+-      PINCTRL_PIN(40, "gpio27"),
+-      PINCTRL_PIN(41, "gpio28"),
+-      PINCTRL_PIN(42, "gpio29"),
+-      PINCTRL_PIN(43, "gpio30"),
+-      PINCTRL_PIN(44, "gpio31"),
+-      PINCTRL_PIN(45, "gpio32"),
+-      PINCTRL_PIN(46, "gpio33"),
+-      PINCTRL_PIN(47, "gpio34"),
+-      PINCTRL_PIN(48, "gpio35"),
+-      PINCTRL_PIN(49, "gpio36"),
+-      PINCTRL_PIN(50, "gpio37"),
+-      PINCTRL_PIN(51, "gpio38"),
+-      PINCTRL_PIN(52, "gpio39"),
+-      PINCTRL_PIN(53, "gpio40"),
+-      PINCTRL_PIN(54, "gpio41"),
+-      PINCTRL_PIN(55, "gpio42"),
+-      PINCTRL_PIN(56, "gpio43"),
+-      PINCTRL_PIN(57, "gpio44"),
+-      PINCTRL_PIN(58, "gpio45"),
+-      PINCTRL_PIN(59, "gpio46"),
+-      PINCTRL_PIN(60, "pcie_reset0"),
+-      PINCTRL_PIN(61, "pcie_reset1"),
+-      PINCTRL_PIN(62, "pcie_reset2"),
+-};
+-
+-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+-static const int en7581_pon_tod_1pps_pins[] = { 46 };
+-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+-static const int en7581_sipo_pins[] = { 16, 17 };
+-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+-static const int en7581_mdio_pins[] = { 14, 15 };
+-static const int en7581_uart2_pins[] = { 48, 55 };
+-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+-static const int en7581_hsuart_pins[] = { 28, 29 };
+-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+-static const int en7581_uart4_pins[] = { 38, 39 };
+-static const int en7581_uart5_pins[] = { 18, 19 };
+-static const int en7581_i2c0_pins[] = { 2, 3 };
+-static const int en7581_i2c1_pins[] = { 14, 15 };
+-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+-static const int en7581_spi_quad_pins[] = { 32, 33 };
+-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+-static const int en7581_spi_cs1_pins[] = { 34 };
+-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+-static const int en7581_pcm_spi_int_pins[] = { 14 };
+-static const int en7581_pcm_spi_rst_pins[] = { 15 };
+-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+-static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 };
+-static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 };
+-static const int en7581_gpio0_pins[] = { 13 };
+-static const int en7581_gpio1_pins[] = { 14 };
+-static const int en7581_gpio2_pins[] = { 15 };
+-static const int en7581_gpio3_pins[] = { 16 };
+-static const int en7581_gpio4_pins[] = { 17 };
+-static const int en7581_gpio5_pins[] = { 18 };
+-static const int en7581_gpio6_pins[] = { 19 };
+-static const int en7581_gpio7_pins[] = { 20 };
+-static const int en7581_gpio8_pins[] = { 21 };
+-static const int en7581_gpio9_pins[] = { 22 };
+-static const int en7581_gpio10_pins[] = { 23 };
+-static const int en7581_gpio11_pins[] = { 24 };
+-static const int en7581_gpio12_pins[] = { 25 };
+-static const int en7581_gpio13_pins[] = { 26 };
+-static const int en7581_gpio14_pins[] = { 27 };
+-static const int en7581_gpio15_pins[] = { 28 };
+-static const int en7581_gpio16_pins[] = { 29 };
+-static const int en7581_gpio17_pins[] = { 30 };
+-static const int en7581_gpio18_pins[] = { 31 };
+-static const int en7581_gpio19_pins[] = { 32 };
+-static const int en7581_gpio20_pins[] = { 33 };
+-static const int en7581_gpio21_pins[] = { 34 };
+-static const int en7581_gpio22_pins[] = { 35 };
+-static const int en7581_gpio23_pins[] = { 36 };
+-static const int en7581_gpio24_pins[] = { 37 };
+-static const int en7581_gpio25_pins[] = { 38 };
+-static const int en7581_gpio26_pins[] = { 39 };
+-static const int en7581_gpio27_pins[] = { 40 };
+-static const int en7581_gpio28_pins[] = { 41 };
+-static const int en7581_gpio29_pins[] = { 42 };
+-static const int en7581_gpio30_pins[] = { 43 };
+-static const int en7581_gpio31_pins[] = { 44 };
+-static const int en7581_gpio32_pins[] = { 45 };
+-static const int en7581_gpio33_pins[] = { 46 };
+-static const int en7581_gpio34_pins[] = { 47 };
+-static const int en7581_gpio35_pins[] = { 48 };
+-static const int en7581_gpio36_pins[] = { 49 };
+-static const int en7581_gpio37_pins[] = { 50 };
+-static const int en7581_gpio38_pins[] = { 51 };
+-static const int en7581_gpio39_pins[] = { 52 };
+-static const int en7581_gpio40_pins[] = { 53 };
+-static const int en7581_gpio41_pins[] = { 54 };
+-static const int en7581_gpio42_pins[] = { 55 };
+-static const int en7581_gpio43_pins[] = { 56 };
+-static const int en7581_gpio44_pins[] = { 57 };
+-static const int en7581_gpio45_pins[] = { 58 };
+-static const int en7581_gpio46_pins[] = { 59 };
+-static const int en7581_gpio47_pins[] = { 60 };
+-static const int en7581_gpio48_pins[] = { 61 };
+-static const int en7581_gpio49_pins[] = { 62 };
+-static const int en7581_pcie_reset0_pins[] = { 60 };
+-static const int en7581_pcie_reset1_pins[] = { 61 };
+-static const int en7581_pcie_reset2_pins[] = { 62 };
+-
+-static const struct pingroup en7581_pinctrl_groups[] = {
+-      PINCTRL_PIN_GROUP("pon", en7581_pon),
+-      PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+-      PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+-      PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+-      PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+-      PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+-      PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+-      PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+-      PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+-      PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+-      PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+-      PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+-      PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+-      PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+-      PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+-      PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+-      PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+-      PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+-      PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+-      PINCTRL_PIN_GROUP("spi", en7581_spi),
+-      PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+-      PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+-      PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+-      PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+-      PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+-      PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+-      PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+-      PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+-      PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+-      PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+-      PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+-      PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+-      PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+-      PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+-      PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+-      PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+-      PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+-      PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+-      PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+-      PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+-      PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+-      PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+-      PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+-      PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+-      PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+-      PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+-      PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+-      PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+-      PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+-      PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+-      PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+-      PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+-      PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+-      PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+-      PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+-      PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+-      PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+-      PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+-      PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
+-      PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+-      PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+-      PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+-      PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+-      PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+-      PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+-      PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+-      PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+-      PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+-      PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+-      PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+-      PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+-      PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+-      PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+-      PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
+-      PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
+-      PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
+-      PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+-      PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+-      PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
+-};
+-
+-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
+-      PINCTRL_PIN(2, "gpio0"),
+-      PINCTRL_PIN(3, "gpio1"),
+-      PINCTRL_PIN(4, "gpio2"),
+-      PINCTRL_PIN(5, "gpio3"),
+-      PINCTRL_PIN(6, "gpio4"),
+-      PINCTRL_PIN(7, "gpio5"),
+-      PINCTRL_PIN(8, "gpio6"),
+-      PINCTRL_PIN(9, "gpio7"),
+-      PINCTRL_PIN(10, "gpio8"),
+-      PINCTRL_PIN(11, "gpio9"),
+-      PINCTRL_PIN(12, "gpio10"),
+-      PINCTRL_PIN(13, "gpio11"),
+-      PINCTRL_PIN(14, "gpio12"),
+-      PINCTRL_PIN(15, "gpio13"),
+-      PINCTRL_PIN(16, "gpio14"),
+-      PINCTRL_PIN(17, "gpio15"),
+-      PINCTRL_PIN(18, "gpio16"),
+-      PINCTRL_PIN(19, "gpio17"),
+-      PINCTRL_PIN(20, "gpio18"),
+-      PINCTRL_PIN(21, "gpio19"),
+-      PINCTRL_PIN(22, "gpio20"),
+-      PINCTRL_PIN(23, "gpio21"),
+-      PINCTRL_PIN(24, "gpio22"),
+-      PINCTRL_PIN(25, "gpio23"),
+-      PINCTRL_PIN(26, "gpio24"),
+-      PINCTRL_PIN(27, "gpio25"),
+-      PINCTRL_PIN(28, "gpio26"),
+-      PINCTRL_PIN(29, "gpio27"),
+-      PINCTRL_PIN(30, "gpio28"),
+-      PINCTRL_PIN(31, "gpio29"),
+-      PINCTRL_PIN(32, "gpio30"),
+-      PINCTRL_PIN(33, "gpio31"),
+-      PINCTRL_PIN(34, "gpio32"),
+-      PINCTRL_PIN(35, "gpio33"),
+-      PINCTRL_PIN(36, "gpio34"),
+-      PINCTRL_PIN(37, "gpio35"),
+-      PINCTRL_PIN(38, "gpio36"),
+-      PINCTRL_PIN(39, "gpio37"),
+-      PINCTRL_PIN(40, "gpio38"),
+-      PINCTRL_PIN(41, "i2c0_scl"),
+-      PINCTRL_PIN(42, "i2c0_sda"),
+-      PINCTRL_PIN(43, "i2c1_scl"),
+-      PINCTRL_PIN(44, "i2c1_sda"),
+-      PINCTRL_PIN(45, "spi_clk"),
+-      PINCTRL_PIN(46, "spi_cs"),
+-      PINCTRL_PIN(47, "spi_mosi"),
+-      PINCTRL_PIN(48, "spi_miso"),
+-      PINCTRL_PIN(49, "uart_txd"),
+-      PINCTRL_PIN(50, "uart_rxd"),
+-      PINCTRL_PIN(51, "pcie_reset0"),
+-      PINCTRL_PIN(52, "pcie_reset1"),
+-      PINCTRL_PIN(53, "mdc_0"),
+-      PINCTRL_PIN(54, "mdio_0"),
+-};
+-
+-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+-static const int an7583_pon_tod_1pps_pins[] = { 32 };
+-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+-static const int an7583_sipo_pins[] = { 34, 35 };
+-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+-static const int an7583_mdio_pins[] = { 53, 54 };
+-static const int an7583_mdio1_pins[] = { 43, 44 };
+-static const int an7583_uart2_pins[] = { 34, 35 };
+-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+-static const int an7583_hsuart_pins[] = { 30, 31 };
+-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+-static const int an7583_npu_uart_pins[] = { 7, 8 };
+-static const int an7583_uart4_pins[] = { 7, 8 };
+-static const int an7583_uart5_pins[] = { 23, 24 };
+-static const int an7583_i2c0_pins[] = { 41, 42 };
+-static const int an7583_i2c1_pins[] = { 43, 44 };
+-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+-static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
+-static const int an7583_spi_quad_pins[] = { 25, 26 };
+-static const int an7583_spi_cs1_pins[] = { 27 };
+-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+-static const int an7583_pcm_spi_rst_pins[] = { 14 };
+-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+-static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 };
+-static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 };
+-static const int an7583_gpio0_pins[] = { 2 };
+-static const int an7583_gpio1_pins[] = { 3 };
+-static const int an7583_gpio2_pins[] = { 4 };
+-static const int an7583_gpio3_pins[] = { 5 };
+-static const int an7583_gpio4_pins[] = { 6 };
+-static const int an7583_gpio5_pins[] = { 7 };
+-static const int an7583_gpio6_pins[] = { 8 };
+-static const int an7583_gpio7_pins[] = { 9 };
+-static const int an7583_gpio8_pins[] = { 10 };
+-static const int an7583_gpio9_pins[] = { 11 };
+-static const int an7583_gpio10_pins[] = { 12 };
+-static const int an7583_gpio11_pins[] = { 13 };
+-static const int an7583_gpio12_pins[] = { 14 };
+-static const int an7583_gpio13_pins[] = { 15 };
+-static const int an7583_gpio14_pins[] = { 16 };
+-static const int an7583_gpio15_pins[] = { 17 };
+-static const int an7583_gpio16_pins[] = { 18 };
+-static const int an7583_gpio17_pins[] = { 19 };
+-static const int an7583_gpio18_pins[] = { 20 };
+-static const int an7583_gpio19_pins[] = { 21 };
+-static const int an7583_gpio20_pins[] = { 22 };
+-static const int an7583_gpio21_pins[] = { 23 };
+-static const int an7583_gpio22_pins[] = { 24 };
+-static const int an7583_gpio23_pins[] = { 25 };
+-static const int an7583_gpio24_pins[] = { 26 };
+-static const int an7583_gpio25_pins[] = { 27 };
+-static const int an7583_gpio26_pins[] = { 28 };
+-static const int an7583_gpio27_pins[] = { 29 };
+-static const int an7583_gpio28_pins[] = { 30 };
+-static const int an7583_gpio29_pins[] = { 31 };
+-static const int an7583_gpio30_pins[] = { 32 };
+-static const int an7583_gpio31_pins[] = { 33 };
+-static const int an7583_gpio32_pins[] = { 34 };
+-static const int an7583_gpio33_pins[] = { 35 };
+-static const int an7583_gpio34_pins[] = { 36 };
+-static const int an7583_gpio35_pins[] = { 37 };
+-static const int an7583_gpio36_pins[] = { 38 };
+-static const int an7583_gpio37_pins[] = { 39 };
+-static const int an7583_gpio38_pins[] = { 40 };
+-static const int an7583_gpio39_pins[] = { 41 };
+-static const int an7583_gpio40_pins[] = { 42 };
+-static const int an7583_gpio41_pins[] = { 43 };
+-static const int an7583_gpio42_pins[] = { 44 };
+-static const int an7583_gpio43_pins[] = { 45 };
+-static const int an7583_gpio44_pins[] = { 46 };
+-static const int an7583_gpio45_pins[] = { 47 };
+-static const int an7583_gpio46_pins[] = { 48 };
+-static const int an7583_gpio47_pins[] = { 49 };
+-static const int an7583_gpio48_pins[] = { 50 };
+-static const int an7583_gpio49_pins[] = { 51 };
+-static const int an7583_gpio50_pins[] = { 52 };
+-static const int an7583_gpio51_pins[] = { 53 };
+-static const int an7583_gpio52_pins[] = { 54 };
+-static const int an7583_pcie_reset0_pins[] = { 51 };
+-static const int an7583_pcie_reset1_pins[] = { 52 };
+-
+-static const struct pingroup an7583_pinctrl_groups[] = {
+-      PINCTRL_PIN_GROUP("pon", an7583_pon),
+-      PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+-      PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+-      PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+-      PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+-      PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+-      PINCTRL_PIN_GROUP("mdio1", an7583_mdio1),
+-      PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+-      PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+-      PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+-      PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+-      PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+-      PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+-      PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+-      PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+-      PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+-      PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+-      PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+-      PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+-      PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+-      PINCTRL_PIN_GROUP("spi", an7583_spi),
+-      PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+-      PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+-      PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+-      PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+-      PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+-      PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+-      PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+-      PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+-      PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+-      PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+-      PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+-      PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+-      PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+-      PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+-      PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+-      PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+-      PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+-      PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+-      PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+-      PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+-      PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+-      PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+-      PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+-      PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+-      PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+-      PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+-      PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+-      PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
+-      PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+-      PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+-      PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+-      PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+-      PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+-      PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+-      PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+-      PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+-      PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+-      PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
+-      PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+-      PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+-      PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+-      PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+-      PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+-      PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+-      PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+-      PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+-      PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+-      PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+-      PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+-      PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+-      PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+-      PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+-      PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+-      PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+-      PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+-      PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+-      PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+-      PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+-      PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+-      PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
+-};
+-
+-static const char *const pon_groups[] = { "pon" };
+-static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" };
+-static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+-static const char *const mdio_groups[] = { "mdio" };
+-static const char *const an7583_mdio_groups[] = { "mdio" };
+-static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart",
+-                                         "hsuart_cts_rts", "uart4",
+-                                         "uart5" };
+-static const char *const i2c_groups[] = { "i2c1" };
+-static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" };
+-static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+-static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+-static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+-static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
+-                                            "pcm_spi_rst", "pcm_spi_cs1",
+-                                            "pcm_spi_cs2_p156",
+-                                            "pcm_spi_cs2_p128",
+-                                            "pcm_spi_cs3", "pcm_spi_cs4" };
+-static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
+-                                                   "pcm_spi_rst", "pcm_spi_cs1" };
+-static const char *const i2s_groups[] = { "i2s" };
+-static const char *const emmc_groups[] = { "emmc" };
+-static const char *const pnand_groups[] = { "pnand" };
+-static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
+-static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
+-                                               "pcie_reset2" };
+-static const char *const an7583_gpio_groups[] = { "gpio39", "gpio40", "gpio41",
+-                                                "gpio42", "gpio43", "gpio44",
+-                                                "gpio45", "gpio46", "gpio47",
+-                                                "gpio48", "gpio49", "gpio50",
+-                                                "gpio51", "gpio52" };
+-static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
+-static const char *const pwm_groups[] = { "gpio0", "gpio1",
+-                                        "gpio2", "gpio3",
+-                                        "gpio4", "gpio5",
+-                                        "gpio6", "gpio7",
+-                                        "gpio8", "gpio9",
+-                                        "gpio10", "gpio11",
+-                                        "gpio12", "gpio13",
+-                                        "gpio14", "gpio15",
+-                                        "gpio16", "gpio17",
+-                                        "gpio18", "gpio19",
+-                                        "gpio20", "gpio21",
+-                                        "gpio22", "gpio23",
+-                                        "gpio24", "gpio25",
+-                                        "gpio26", "gpio27",
+-                                        "gpio28", "gpio29",
+-                                        "gpio30", "gpio31",
+-                                        "gpio36", "gpio37",
+-                                        "gpio38", "gpio39",
+-                                        "gpio40", "gpio41",
+-                                        "gpio42", "gpio43",
+-                                        "gpio44", "gpio45",
+-                                        "gpio46", "gpio47",
+-                                        "gpio48", "gpio49" };
+-static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
+-                                               "gpio2", "gpio3",
+-                                               "gpio4", "gpio5",
+-                                               "gpio6", "gpio7",
+-                                               "gpio8", "gpio9",
+-                                               "gpio10", "gpio11",
+-                                               "gpio12", "gpio13",
+-                                               "gpio14", "gpio15",
+-                                               "gpio16", "gpio17",
+-                                               "gpio18", "gpio19",
+-                                               "gpio20", "gpio21",
+-                                               "gpio22", "gpio23",
+-                                               "gpio24", "gpio25",
+-                                               "gpio26", "gpio27",
+-                                               "gpio28", "gpio29",
+-                                               "gpio30", "gpio31",
+-                                               "gpio36", "gpio37",
+-                                               "gpio38", "gpio39",
+-                                               "gpio40", "gpio41",
+-                                               "gpio42", "gpio43",
+-                                               "gpio44", "gpio45",
+-                                               "gpio46", "gpio47",
+-                                               "gpio48", "gpio49",
+-                                               "gpio50", "gpio51" };
+-static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
+-                                              "gpio35", "gpio42" };
+-static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
+-                                              "gpio35", "gpio42" };
+-static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
+-                                              "gpio35", "gpio42" };
+-static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
+-                                              "gpio35", "gpio42" };
+-static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
+-                                              "gpio45", "gpio46" };
+-static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
+-                                              "gpio45", "gpio46" };
+-static const char *const phy3_led1_groups[] = { "gpio43", "gpio44",
+-                                              "gpio45", "gpio46" };
+-static const char *const phy4_led1_groups[] = { "gpio43", "gpio44",
+-                                              "gpio45", "gpio46" };
+-static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2",
+-                                                      "gpio3", "gpio4" };
+-static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2",
+-                                                      "gpio3", "gpio4" };
+-static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2",
+-                                                      "gpio3", "gpio4" };
+-static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2",
+-                                                      "gpio3", "gpio4" };
+-static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9",
+-                                                      "gpio10", "gpio11" };
+-static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9",
+-                                                      "gpio10", "gpio11" };
+-static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9",
+-                                                      "gpio10", "gpio11" };
+-static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9",
+-                                                      "gpio10", "gpio11" };
+-
+-static const struct airoha_pinctrl_func_group pon_func_group[] = {
+-      {
+-              .name = "pon",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PON_MODE_MASK,
+-                      GPIO_PON_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+-      {
+-              .name = "pon_tod_1pps",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
+-                      PON_TOD_1PPS_MODE_MASK,
+-                      PON_TOD_1PPS_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "gsw_tod_1pps",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
+-                      GSW_TOD_1PPS_MODE_MASK,
+-                      GSW_TOD_1PPS_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group sipo_func_group[] = {
+-      {
+-              .name = "sipo",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+-                      GPIO_SIPO_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "sipo_rclk",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
+-                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+-      {
+-              .name = "mdio",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
+-                      GPIO_MDC_IO_MASTER_MODE_MASK,
+-                      GPIO_MDC_IO_MASTER_MODE_MASK
+-              },
+-              .regmap[1] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_FORCE_GPIO_EN,
+-                      FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
+-                      FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
+-              },
+-              .regmap_size = 2,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
+-      {
+-              .name = "mdio",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group uart_func_group[] = {
+-      {
+-              .name = "uart2",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_UART2_MODE_MASK,
+-                      GPIO_UART2_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "uart2_cts_rts",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
+-                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "hsuart",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+-                      GPIO_HSUART_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-      {
+-              .name = "hsuart_cts_rts",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
+-                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "uart4",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_UART4_MODE_MASK,
+-                      GPIO_UART4_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "uart5",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_UART5_MODE_MASK,
+-                      GPIO_UART5_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+-      {
+-              .name = "i2c1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
+-                      GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE,
+-                      GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE,
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = {
+-      {
+-              .name = "i2c0",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "i2c1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group jtag_func_group[] = {
+-      {
+-              .name = "jtag_udi",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_NPU_UART_EN,
+-                      JTAG_UDI_EN_MASK,
+-                      JTAG_UDI_EN_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "jtag_dfd",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_NPU_UART_EN,
+-                      JTAG_DFD_EN_MASK,
+-                      JTAG_DFD_EN_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group pcm_func_group[] = {
+-      {
+-              .name = "pcm1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM1_MODE_MASK,
+-                      GPIO_PCM1_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm2",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM2_MODE_MASK,
+-                      GPIO_PCM2_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group spi_func_group[] = {
+-      {
+-              .name = "spi_quad",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_SPI_QUAD_MODE_MASK,
+-                      GPIO_SPI_QUAD_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "spi_cs1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_SPI_CS1_MODE_MASK,
+-                      GPIO_SPI_CS1_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "spi_cs2",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_SPI_CS2_MODE_MASK,
+-                      GPIO_SPI_CS2_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "spi_cs3",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_SPI_CS3_MODE_MASK,
+-                      GPIO_SPI_CS3_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "spi_cs4",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_SPI_CS4_MODE_MASK,
+-                      GPIO_SPI_CS4_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+-      {
+-              .name = "pcm_spi",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_MODE_MASK,
+-                      GPIO_PCM_SPI_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_int",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_INT_MODE_MASK,
+-                      GPIO_PCM_INT_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_rst",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_RESET_MODE_MASK,
+-                      GPIO_PCM_RESET_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS1_MODE_MASK,
+-                      GPIO_PCM_SPI_CS1_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs2_p128",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS2_MODE_P128_MASK,
+-                      GPIO_PCM_SPI_CS2_MODE_P128_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs2_p156",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS2_MODE_P156_MASK,
+-                      GPIO_PCM_SPI_CS2_MODE_P156_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs3",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS3_MODE_MASK,
+-                      GPIO_PCM_SPI_CS3_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs4",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS4_MODE_MASK,
+-                      GPIO_PCM_SPI_CS4_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
+-      {
+-              .name = "pcm_spi",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_MODE_MASK,
+-                      GPIO_PCM_SPI_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_int",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_INT_MODE_MASK,
+-                      GPIO_PCM_INT_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_rst",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_RESET_MODE_MASK,
+-                      GPIO_PCM_RESET_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS1_MODE_MASK,
+-                      GPIO_PCM_SPI_CS1_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs2",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+-                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs3",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS3_MODE_MASK,
+-                      GPIO_PCM_SPI_CS3_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcm_spi_cs4",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_SPI_CS1_MODE,
+-                      GPIO_PCM_SPI_CS4_MODE_MASK,
+-                      GPIO_PCM_SPI_CS4_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group i2s_func_group[] = {
+-      {
+-              .name = "i2s",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
+-                      GPIO_I2S_MODE_MASK,
+-                      GPIO_I2S_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group emmc_func_group[] = {
+-      {
+-              .name = "emmc",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_EMMC_MODE_MASK,
+-                      GPIO_EMMC_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group pnand_func_group[] = {
+-      {
+-              .name = "pnand",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PARALLEL_NAND_MODE_MASK,
+-                      GPIO_PARALLEL_NAND_MODE_MASK
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+-      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+-                              GPIO_PCIE_RESET0_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+-                              GPIO_PCIE_RESET1_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+-                              GPIO_PCIE_RESET2_MASK),
+-};
+-
+-static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+-      {
+-              .name = "pcie_reset0",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PCIE_RESET0_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcie_reset1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PCIE_RESET1_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcie_reset2",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PCIE_RESET2_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
+-      AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+-                              AN7583_I2C0_SCL_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+-                              AN7583_I2C0_SDA_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+-                              AN7583_I2C1_SCL_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+-                              AN7583_I2C1_SDA_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+-                              AN7583_SPI_CLK_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+-                              AN7583_SPI_CS_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+-                              AN7583_SPI_MOSI_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+-                              AN7583_SPI_MISO_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+-                              AN7583_UART_TXD_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+-                              AN7583_UART_RXD_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+-                              GPIO_PCIE_RESET0_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+-                              GPIO_PCIE_RESET1_MASK),
+-      AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+-                              AN7583_MDC_0_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
+-      {
+-              .name = "pcie_reset0",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PCIE_RESET0_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      }, {
+-              .name = "pcie_reset1",
+-              .regmap[0] = {
+-                      AIROHA_FUNC_MUX,
+-                      REG_GPIO_PON_MODE,
+-                      GPIO_PCIE_RESET1_MASK,
+-                      0
+-              },
+-              .regmap_size = 1,
+-      },
+-};
+-
+-static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+-      AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+-                                 GPIO_PCIE_RESET0_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+-                                 GPIO_PCIE_RESET1_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+-                                 GPIO_PCIE_RESET2_MASK),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
+-      AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+-                                 AN7583_I2C0_SCL_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+-                                 AN7583_I2C0_SDA_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+-                                 AN7583_I2C1_SCL_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+-                                 AN7583_I2C1_SDA_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+-                                 AN7583_SPI_CLK_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+-                                 AN7583_SPI_CS_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+-                                 AN7583_SPI_MOSI_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+-                                 AN7583_SPI_MISO_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+-                                 AN7583_UART_TXD_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+-                                 AN7583_UART_RXD_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+-                                 GPIO_PCIE_RESET0_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+-                                 GPIO_PCIE_RESET1_MASK),
+-      AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+-                                 AN7583_MDC_0_GPIO_MODE_MASK),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+-};
+-
+-static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+-};
+-
+-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
+-      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+-                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+-                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
+-                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
+-      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
+-                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+-};
+-
+-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
+-      PINCTRL_FUNC_DESC("pon", pon),
+-      PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+-      PINCTRL_FUNC_DESC("sipo", sipo),
+-      PINCTRL_FUNC_DESC("mdio", mdio),
+-      PINCTRL_FUNC_DESC("uart", uart),
+-      PINCTRL_FUNC_DESC("i2c", i2c),
+-      PINCTRL_FUNC_DESC("jtag", jtag),
+-      PINCTRL_FUNC_DESC("pcm", pcm),
+-      PINCTRL_FUNC_DESC("spi", spi),
+-      PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+-      PINCTRL_FUNC_DESC("i2s", i2s),
+-      PINCTRL_FUNC_DESC("emmc", emmc),
+-      PINCTRL_FUNC_DESC("pnand", pnand),
+-      PINCTRL_FUNC_DESC("gpio", gpio),
+-      PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
+-      PINCTRL_FUNC_DESC("pwm", pwm),
+-      PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
+-      PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
+-      PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
+-      PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
+-      PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
+-      PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
+-      PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
+-      PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+-};
+-
+-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
+-      PINCTRL_FUNC_DESC("pon", pon),
+-      PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+-      PINCTRL_FUNC_DESC("sipo", sipo),
+-      PINCTRL_FUNC_DESC("mdio", an7583_mdio),
+-      PINCTRL_FUNC_DESC("uart", uart),
+-      PINCTRL_FUNC_DESC("i2c", an7583_i2c),
+-      PINCTRL_FUNC_DESC("jtag", jtag),
+-      PINCTRL_FUNC_DESC("pcm", pcm),
+-      PINCTRL_FUNC_DESC("spi", spi),
+-      PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
+-      PINCTRL_FUNC_DESC("emmc", emmc),
+-      PINCTRL_FUNC_DESC("pnand", pnand),
+-      PINCTRL_FUNC_DESC("gpio", an7583_gpio),
+-      PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+-      PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+-      PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+-      PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+-      PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+-      PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+-      PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+-      PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+-      PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+-      PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
+-};
+-
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
+-      PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+-      PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+-      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+-      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+-      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+-      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
+-      PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
+-      PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
+-      PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
+-      PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
+-      PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
+-      PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
+-      PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
+-      PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
+-      PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
+-      PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
+-      PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
+-      PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
+-      PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
+-      PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
+-      PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
+-      PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
+-      PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
+-      PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
+-      PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
+-      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
+-      PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+-      PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+-      PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+-      PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
+-      PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
+-      PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
+-      PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
+-      PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
+-      PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
+-      PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
+-      PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+-      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+-      PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
+-      PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+-      PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+-      PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+-      PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
+-      PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+-      PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+-      PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
+-      PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+-      PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+-      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+-      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+-      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+-      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
+-      PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
+-      PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
+-      PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
+-      PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
+-      PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
+-      PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
+-      PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
+-      PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
+-      PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
+-      PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
+-      PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
+-      PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
+-      PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
+-      PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
+-      PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
+-      PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
+-      PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
+-      PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
+-      PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
+-      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
+-      PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+-      PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+-      PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+-      PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
+-      PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
+-      PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
+-      PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
+-      PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
+-      PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
+-      PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
+-      PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+-      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+-      PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
+-      PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+-      PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+-      PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+-      PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
+-      PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+-      PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+-      PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
+-      PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+-      PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+-      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+-      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+-      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+-      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
+-      PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
+-      PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
+-      PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
+-      PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
+-      PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
+-      PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
+-      PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
+-      PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
+-      PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
+-      PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
+-      PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
+-      PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
+-      PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
+-      PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
+-      PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
+-      PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
+-      PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
+-      PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
+-      PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
+-      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
+-      PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+-      PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+-      PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+-      PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
+-      PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
+-      PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
+-      PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
+-      PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
+-      PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
+-      PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
+-      PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+-      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+-      PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
+-      PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+-      PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+-      PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+-      PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
+-      PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+-      PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+-      PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
+-      PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+-      PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+-      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+-      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+-      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+-      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+-      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+-      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
+-      PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
+-      PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
+-      PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
+-      PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
+-      PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
+-      PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
+-      PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
+-      PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
+-      PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
+-      PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
+-      PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
+-      PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
+-      PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
+-      PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
+-      PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
+-      PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
+-      PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
+-      PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
+-      PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
+-      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
+-      PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+-      PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+-      PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+-      PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
+-      PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
+-      PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
+-      PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
+-      PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
+-      PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
+-      PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
+-      PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
+-      PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
+-      PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
+-      PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
+-      PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
+-      PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
+-      PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
+-      PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
+-      PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
+-      PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
+-      PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
+-      PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
+-      PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
+-      PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
+-      PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
+-      PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
+-      PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
+-      PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
+-      PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
+-      PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
+-      PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
+-      PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
+-      PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
+-      PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
+-      PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
+-      PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
+-      PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
+-      PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
+-      PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+-      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+-      PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
+-      PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+-      PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+-      PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+-      PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
+-      PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+-      PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+-      PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
+-      PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+-      PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+-      PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+-};
+-
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
+-      PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+-      PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+-};
+-
+ static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev,
+                                           struct pinctrl_gpio_range *range,
+                                           int pin)
+@@ -3061,7 +772,7 @@ static const struct pinctrl_ops airoha_p
+       .dt_free_map = pinconf_generic_dt_free_map,
+ };
+ 
+-static int airoha_pinctrl_probe(struct platform_device *pdev)
++int airoha_pinctrl_probe(struct platform_device *pdev)
+ {
+       const struct airoha_pinctrl_match_data *data;
+       struct device *dev = &pdev->dev;
+@@ -3070,6 +781,8 @@ static int airoha_pinctrl_probe(struct p
+       int err, i;
+ 
+       data = device_get_match_data(dev);
++      if (!data)
++              return -EINVAL;
+ 
+       pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL);
+       if (!pinctrl)
+@@ -3086,8 +799,8 @@ static int airoha_pinctrl_probe(struct p
+       pinctrl->chip_scu = map;
+ 
+       /* Init pinctrl desc struct */
+-      pinctrl->desc.name = KBUILD_MODNAME;
+-      pinctrl->desc.owner = THIS_MODULE;
++      pinctrl->desc.name = data->pinctrl_name;
++      pinctrl->desc.owner = data->pinctrl_owner;
+       pinctrl->desc.pctlops = &airoha_pctlops;
+       pinctrl->desc.pmxops = &airoha_pmxops;
+       pinctrl->desc.confops = &airoha_confops;
+@@ -3141,87 +854,10 @@ static int airoha_pinctrl_probe(struct p
+       /* build gpio-chip */
+       return airoha_pinctrl_add_gpiochip(pinctrl, pdev);
+ }
+-
+-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
+-      .pins = en7581_pinctrl_pins,
+-      .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+-      .grps = en7581_pinctrl_groups,
+-      .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+-      .funcs = en7581_pinctrl_funcs,
+-      .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
+-      .confs_info = {
+-              [AIROHA_PINCTRL_CONFS_PULLUP] = {
+-                      .confs = en7581_pinctrl_pullup_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+-                      .confs = en7581_pinctrl_pulldown_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+-                      .confs = en7581_pinctrl_drive_e2_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+-                      .confs = en7581_pinctrl_drive_e4_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+-                      .confs = en7581_pinctrl_pcie_rst_od_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
+-              },
+-      },
+-};
+-
+-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
+-      .pins = an7583_pinctrl_pins,
+-      .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+-      .grps = an7583_pinctrl_groups,
+-      .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+-      .funcs = an7583_pinctrl_funcs,
+-      .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
+-      .confs_info = {
+-              [AIROHA_PINCTRL_CONFS_PULLUP] = {
+-                      .confs = an7583_pinctrl_pullup_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+-                      .confs = an7583_pinctrl_pulldown_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+-                      .confs = an7583_pinctrl_drive_e2_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+-                      .confs = an7583_pinctrl_drive_e4_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
+-              },
+-              [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+-                      .confs = an7583_pinctrl_pcie_rst_od_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
+-              },
+-      },
+-};
+-
+-static const struct of_device_id airoha_pinctrl_of_match[] = {
+-      { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
+-      { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
+-      { /* sentinel */ }
+-};
+-MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
+-
+-static struct platform_driver airoha_pinctrl_driver = {
+-      .probe = airoha_pinctrl_probe,
+-      .driver = {
+-              .name = "pinctrl-airoha",
+-              .of_match_table = airoha_pinctrl_of_match,
+-      },
+-};
+-module_platform_driver(airoha_pinctrl_driver);
++EXPORT_SYMBOL_GPL(airoha_pinctrl_probe);
+ 
+ MODULE_LICENSE("GPL");
+ MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
+ MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
+ MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
+-MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
++MODULE_DESCRIPTION("Pinctrl common driver for Airoha SoC");
+--- /dev/null
++++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
+@@ -0,0 +1,1486 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
++ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
++ * Author: Markus Gothe <markus.gothe@genexis.eu>
++ */
++
++#include "airoha-common.h"
++
++/* MUX */
++#define REG_GPIO_2ND_I2C_MODE                 0x0214
++#define GPIO_MDC_IO_MASTER_MODE_MASK          BIT(14)
++#define GPIO_I2C_MASTER_MODE_MODE             BIT(13)
++#define GPIO_I2S_MODE_MASK                    BIT(12)
++#define GPIO_I2C_SLAVE_MODE_MODE              BIT(11)
++#define GPIO_LAN3_LED1_MODE_MASK              BIT(10)
++#define GPIO_LAN3_LED0_MODE_MASK              BIT(9)
++#define GPIO_LAN2_LED1_MODE_MASK              BIT(8)
++#define GPIO_LAN2_LED0_MODE_MASK              BIT(7)
++#define GPIO_LAN1_LED1_MODE_MASK              BIT(6)
++#define GPIO_LAN1_LED0_MODE_MASK              BIT(5)
++#define GPIO_LAN0_LED1_MODE_MASK              BIT(4)
++#define GPIO_LAN0_LED0_MODE_MASK              BIT(3)
++#define PON_TOD_1PPS_MODE_MASK                        BIT(2)
++#define GSW_TOD_1PPS_MODE_MASK                        BIT(1)
++#define GPIO_2ND_I2C_MODE_MASK                        BIT(0)
++
++#define REG_GPIO_SPI_CS1_MODE                 0x0218
++#define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
++#define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
++#define GPIO_PCM_SPI_CS2_MODE_P156_MASK               BIT(19)
++#define GPIO_PCM_SPI_CS2_MODE_P128_MASK               BIT(18)
++#define GPIO_PCM_SPI_CS1_MODE_MASK            BIT(17)
++#define GPIO_PCM_SPI_MODE_MASK                        BIT(16)
++#define GPIO_PCM2_MODE_MASK                   BIT(13)
++#define GPIO_PCM1_MODE_MASK                   BIT(12)
++#define GPIO_PCM_INT_MODE_MASK                        BIT(9)
++#define GPIO_PCM_RESET_MODE_MASK              BIT(8)
++#define GPIO_SPI_QUAD_MODE_MASK                       BIT(4)
++#define GPIO_SPI_CS4_MODE_MASK                        BIT(3)
++#define GPIO_SPI_CS3_MODE_MASK                        BIT(2)
++#define GPIO_SPI_CS2_MODE_MASK                        BIT(1)
++#define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
++
++#define REG_GPIO_PON_MODE                     0x021c
++#define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
++#define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
++#define GPIO_PCIE_RESET2_MASK                 BIT(12)
++#define SIPO_RCLK_MODE_MASK                   BIT(11)
++#define GPIO_PCIE_RESET1_MASK                 BIT(10)
++#define GPIO_PCIE_RESET0_MASK                 BIT(9)
++#define GPIO_UART5_MODE_MASK                  BIT(8)
++#define GPIO_UART4_MODE_MASK                  BIT(7)
++#define GPIO_HSUART_CTS_RTS_MODE_MASK         BIT(6)
++#define GPIO_HSUART_MODE_MASK                 BIT(5)
++#define GPIO_UART2_CTS_RTS_MODE_MASK          BIT(4)
++#define GPIO_UART2_MODE_MASK                  BIT(3)
++#define GPIO_SIPO_MODE_MASK                   BIT(2)
++#define GPIO_EMMC_MODE_MASK                   BIT(1)
++#define GPIO_PON_MODE_MASK                    BIT(0)
++
++#define REG_NPU_UART_EN                               0x0224
++#define JTAG_UDI_EN_MASK                      BIT(4)
++#define JTAG_DFD_EN_MASK                      BIT(3)
++
++#define REG_FORCE_GPIO_EN                     0x0228
++#define FORCE_GPIO_EN(n)                      BIT(n)
++
++/* LED MAP */
++#define REG_LAN_LED0_MAPPING                  0x027c
++#define REG_LAN_LED1_MAPPING                  0x0280
++
++#define LAN4_LED_MAPPING_MASK                 GENMASK(18, 16)
++#define LAN4_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
++
++#define LAN3_LED_MAPPING_MASK                 GENMASK(14, 12)
++#define LAN3_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
++
++#define LAN2_LED_MAPPING_MASK                 GENMASK(10, 8)
++#define LAN2_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
++
++#define LAN1_LED_MAPPING_MASK                 GENMASK(6, 4)
++#define LAN1_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
++
++#define LAN0_LED_MAPPING_MASK                 GENMASK(2, 0)
++#define LAN0_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
++
++/* CONF */
++#define REG_I2C_SDA_E2                                0x001c
++#define SPI_MISO_E2_MASK                      BIT(14)
++#define SPI_MOSI_E2_MASK                      BIT(13)
++#define SPI_CLK_E2_MASK                               BIT(12)
++#define SPI_CS0_E2_MASK                               BIT(11)
++#define PCIE2_RESET_E2_MASK                   BIT(10)
++#define PCIE1_RESET_E2_MASK                   BIT(9)
++#define PCIE0_RESET_E2_MASK                   BIT(8)
++#define UART1_RXD_E2_MASK                     BIT(3)
++#define UART1_TXD_E2_MASK                     BIT(2)
++#define I2C_SCL_E2_MASK                               BIT(1)
++#define I2C_SDA_E2_MASK                               BIT(0)
++
++#define REG_I2C_SDA_E4                                0x0020
++#define SPI_MISO_E4_MASK                      BIT(14)
++#define SPI_MOSI_E4_MASK                      BIT(13)
++#define SPI_CLK_E4_MASK                               BIT(12)
++#define SPI_CS0_E4_MASK                               BIT(11)
++#define PCIE2_RESET_E4_MASK                   BIT(10)
++#define PCIE1_RESET_E4_MASK                   BIT(9)
++#define PCIE0_RESET_E4_MASK                   BIT(8)
++#define UART1_RXD_E4_MASK                     BIT(3)
++#define UART1_TXD_E4_MASK                     BIT(2)
++#define I2C_SCL_E4_MASK                               BIT(1)
++#define I2C_SDA_E4_MASK                               BIT(0)
++
++#define REG_GPIO_L_E2                         0x0024
++#define REG_GPIO_L_E4                         0x0028
++#define REG_GPIO_H_E2                         0x002c
++#define REG_GPIO_H_E4                         0x0030
++
++#define REG_I2C_SDA_PU                                0x0044
++#define SPI_MISO_PU_MASK                      BIT(14)
++#define SPI_MOSI_PU_MASK                      BIT(13)
++#define SPI_CLK_PU_MASK                               BIT(12)
++#define SPI_CS0_PU_MASK                               BIT(11)
++#define PCIE2_RESET_PU_MASK                   BIT(10)
++#define PCIE1_RESET_PU_MASK                   BIT(9)
++#define PCIE0_RESET_PU_MASK                   BIT(8)
++#define UART1_RXD_PU_MASK                     BIT(3)
++#define UART1_TXD_PU_MASK                     BIT(2)
++#define I2C_SCL_PU_MASK                               BIT(1)
++#define I2C_SDA_PU_MASK                               BIT(0)
++
++#define REG_I2C_SDA_PD                                0x0048
++#define SPI_MISO_PD_MASK                      BIT(14)
++#define SPI_MOSI_PD_MASK                      BIT(13)
++#define SPI_CLK_PD_MASK                               BIT(12)
++#define SPI_CS0_PD_MASK                               BIT(11)
++#define PCIE2_RESET_PD_MASK                   BIT(10)
++#define PCIE1_RESET_PD_MASK                   BIT(9)
++#define PCIE0_RESET_PD_MASK                   BIT(8)
++#define UART1_RXD_PD_MASK                     BIT(3)
++#define UART1_TXD_PD_MASK                     BIT(2)
++#define I2C_SCL_PD_MASK                               BIT(1)
++#define I2C_SDA_PD_MASK                               BIT(0)
++
++#define REG_GPIO_L_PU                         0x004c
++#define REG_GPIO_L_PD                         0x0050
++#define REG_GPIO_H_PU                         0x0054
++#define REG_GPIO_H_PD                         0x0058
++
++#define REG_PCIE_RESET_OD                     0x018c
++#define PCIE2_RESET_OD_MASK                   BIT(2)
++#define PCIE1_RESET_OD_MASK                   BIT(1)
++#define PCIE0_RESET_OD_MASK                   BIT(0)
++
++/* PWM MODE CONF */
++#define REG_GPIO_FLASH_MODE_CFG                       0x0034
++#define GPIO15_FLASH_MODE_CFG                 BIT(15)
++#define GPIO14_FLASH_MODE_CFG                 BIT(14)
++#define GPIO13_FLASH_MODE_CFG                 BIT(13)
++#define GPIO12_FLASH_MODE_CFG                 BIT(12)
++#define GPIO11_FLASH_MODE_CFG                 BIT(11)
++#define GPIO10_FLASH_MODE_CFG                 BIT(10)
++#define GPIO9_FLASH_MODE_CFG                  BIT(9)
++#define GPIO8_FLASH_MODE_CFG                  BIT(8)
++#define GPIO7_FLASH_MODE_CFG                  BIT(7)
++#define GPIO6_FLASH_MODE_CFG                  BIT(6)
++#define GPIO5_FLASH_MODE_CFG                  BIT(5)
++#define GPIO4_FLASH_MODE_CFG                  BIT(4)
++#define GPIO3_FLASH_MODE_CFG                  BIT(3)
++#define GPIO2_FLASH_MODE_CFG                  BIT(2)
++#define GPIO1_FLASH_MODE_CFG                  BIT(1)
++#define GPIO0_FLASH_MODE_CFG                  BIT(0)
++
++/* PWM MODE CONF EXT */
++#define REG_GPIO_FLASH_MODE_CFG_EXT           0x0068
++#define GPIO51_FLASH_MODE_CFG                 BIT(31)
++#define GPIO50_FLASH_MODE_CFG                 BIT(30)
++#define GPIO49_FLASH_MODE_CFG                 BIT(29)
++#define GPIO48_FLASH_MODE_CFG                 BIT(28)
++#define GPIO47_FLASH_MODE_CFG                 BIT(27)
++#define GPIO46_FLASH_MODE_CFG                 BIT(26)
++#define GPIO45_FLASH_MODE_CFG                 BIT(25)
++#define GPIO44_FLASH_MODE_CFG                 BIT(24)
++#define GPIO43_FLASH_MODE_CFG                 BIT(23)
++#define GPIO42_FLASH_MODE_CFG                 BIT(22)
++#define GPIO41_FLASH_MODE_CFG                 BIT(21)
++#define GPIO40_FLASH_MODE_CFG                 BIT(20)
++#define GPIO39_FLASH_MODE_CFG                 BIT(19)
++#define GPIO38_FLASH_MODE_CFG                 BIT(18)
++#define GPIO37_FLASH_MODE_CFG                 BIT(17)
++#define GPIO36_FLASH_MODE_CFG                 BIT(16)
++#define GPIO31_FLASH_MODE_CFG                 BIT(15)
++#define GPIO30_FLASH_MODE_CFG                 BIT(14)
++#define GPIO29_FLASH_MODE_CFG                 BIT(13)
++#define GPIO28_FLASH_MODE_CFG                 BIT(12)
++#define GPIO27_FLASH_MODE_CFG                 BIT(11)
++#define GPIO26_FLASH_MODE_CFG                 BIT(10)
++#define GPIO25_FLASH_MODE_CFG                 BIT(9)
++#define GPIO24_FLASH_MODE_CFG                 BIT(8)
++#define GPIO23_FLASH_MODE_CFG                 BIT(7)
++#define GPIO22_FLASH_MODE_CFG                 BIT(6)
++#define GPIO21_FLASH_MODE_CFG                 BIT(5)
++#define GPIO20_FLASH_MODE_CFG                 BIT(4)
++#define GPIO19_FLASH_MODE_CFG                 BIT(3)
++#define GPIO18_FLASH_MODE_CFG                 BIT(2)
++#define GPIO17_FLASH_MODE_CFG                 BIT(1)
++#define GPIO16_FLASH_MODE_CFG                 BIT(0)
++
++#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      0                                       \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++/* PWM */
++#define AIROHA_PINCTRL_PWM(gpio, mux_val)                     \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_MUX,                    \
++                      REG_GPIO_FLASH_MODE_CFG,                \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)                 \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED0_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED1_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
++      PINCTRL_PIN(0, "uart1_txd"),
++      PINCTRL_PIN(1, "uart1_rxd"),
++      PINCTRL_PIN(2, "i2c_scl"),
++      PINCTRL_PIN(3, "i2c_sda"),
++      PINCTRL_PIN(4, "spi_cs0"),
++      PINCTRL_PIN(5, "spi_clk"),
++      PINCTRL_PIN(6, "spi_mosi"),
++      PINCTRL_PIN(7, "spi_miso"),
++      PINCTRL_PIN(13, "gpio0"),
++      PINCTRL_PIN(14, "gpio1"),
++      PINCTRL_PIN(15, "gpio2"),
++      PINCTRL_PIN(16, "gpio3"),
++      PINCTRL_PIN(17, "gpio4"),
++      PINCTRL_PIN(18, "gpio5"),
++      PINCTRL_PIN(19, "gpio6"),
++      PINCTRL_PIN(20, "gpio7"),
++      PINCTRL_PIN(21, "gpio8"),
++      PINCTRL_PIN(22, "gpio9"),
++      PINCTRL_PIN(23, "gpio10"),
++      PINCTRL_PIN(24, "gpio11"),
++      PINCTRL_PIN(25, "gpio12"),
++      PINCTRL_PIN(26, "gpio13"),
++      PINCTRL_PIN(27, "gpio14"),
++      PINCTRL_PIN(28, "gpio15"),
++      PINCTRL_PIN(29, "gpio16"),
++      PINCTRL_PIN(30, "gpio17"),
++      PINCTRL_PIN(31, "gpio18"),
++      PINCTRL_PIN(32, "gpio19"),
++      PINCTRL_PIN(33, "gpio20"),
++      PINCTRL_PIN(34, "gpio21"),
++      PINCTRL_PIN(35, "gpio22"),
++      PINCTRL_PIN(36, "gpio23"),
++      PINCTRL_PIN(37, "gpio24"),
++      PINCTRL_PIN(38, "gpio25"),
++      PINCTRL_PIN(39, "gpio26"),
++      PINCTRL_PIN(40, "gpio27"),
++      PINCTRL_PIN(41, "gpio28"),
++      PINCTRL_PIN(42, "gpio29"),
++      PINCTRL_PIN(43, "gpio30"),
++      PINCTRL_PIN(44, "gpio31"),
++      PINCTRL_PIN(45, "gpio32"),
++      PINCTRL_PIN(46, "gpio33"),
++      PINCTRL_PIN(47, "gpio34"),
++      PINCTRL_PIN(48, "gpio35"),
++      PINCTRL_PIN(49, "gpio36"),
++      PINCTRL_PIN(50, "gpio37"),
++      PINCTRL_PIN(51, "gpio38"),
++      PINCTRL_PIN(52, "gpio39"),
++      PINCTRL_PIN(53, "gpio40"),
++      PINCTRL_PIN(54, "gpio41"),
++      PINCTRL_PIN(55, "gpio42"),
++      PINCTRL_PIN(56, "gpio43"),
++      PINCTRL_PIN(57, "gpio44"),
++      PINCTRL_PIN(58, "gpio45"),
++      PINCTRL_PIN(59, "gpio46"),
++      PINCTRL_PIN(60, "pcie_reset0"),
++      PINCTRL_PIN(61, "pcie_reset1"),
++      PINCTRL_PIN(62, "pcie_reset2"),
++};
++
++static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
++static const int en7581_pon_tod_1pps_pins[] = { 46 };
++static const int en7581_gsw_tod_1pps_pins[] = { 46 };
++static const int en7581_sipo_pins[] = { 16, 17 };
++static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
++static const int en7581_mdio_pins[] = { 14, 15 };
++static const int en7581_uart2_pins[] = { 48, 55 };
++static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
++static const int en7581_hsuart_pins[] = { 28, 29 };
++static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
++static const int en7581_uart4_pins[] = { 38, 39 };
++static const int en7581_uart5_pins[] = { 18, 19 };
++static const int en7581_i2c0_pins[] = { 2, 3 };
++static const int en7581_i2c1_pins[] = { 14, 15 };
++static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
++static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
++static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
++static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
++static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
++static const int en7581_spi_quad_pins[] = { 32, 33 };
++static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
++static const int en7581_spi_cs1_pins[] = { 34 };
++static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
++static const int en7581_pcm_spi_int_pins[] = { 14 };
++static const int en7581_pcm_spi_rst_pins[] = { 15 };
++static const int en7581_pcm_spi_cs1_pins[] = { 43 };
++static const int en7581_pcm_spi_cs2_pins[] = { 40 };
++static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
++static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
++static const int en7581_pcm_spi_cs3_pins[] = { 41 };
++static const int en7581_pcm_spi_cs4_pins[] = { 42 };
++static const int en7581_emmc_pins[] = {
++      4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
++};
++static const int en7581_pnand_pins[] = {
++      4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
++};
++static const int en7581_gpio0_pins[] = { 13 };
++static const int en7581_gpio1_pins[] = { 14 };
++static const int en7581_gpio2_pins[] = { 15 };
++static const int en7581_gpio3_pins[] = { 16 };
++static const int en7581_gpio4_pins[] = { 17 };
++static const int en7581_gpio5_pins[] = { 18 };
++static const int en7581_gpio6_pins[] = { 19 };
++static const int en7581_gpio7_pins[] = { 20 };
++static const int en7581_gpio8_pins[] = { 21 };
++static const int en7581_gpio9_pins[] = { 22 };
++static const int en7581_gpio10_pins[] = { 23 };
++static const int en7581_gpio11_pins[] = { 24 };
++static const int en7581_gpio12_pins[] = { 25 };
++static const int en7581_gpio13_pins[] = { 26 };
++static const int en7581_gpio14_pins[] = { 27 };
++static const int en7581_gpio15_pins[] = { 28 };
++static const int en7581_gpio16_pins[] = { 29 };
++static const int en7581_gpio17_pins[] = { 30 };
++static const int en7581_gpio18_pins[] = { 31 };
++static const int en7581_gpio19_pins[] = { 32 };
++static const int en7581_gpio20_pins[] = { 33 };
++static const int en7581_gpio21_pins[] = { 34 };
++static const int en7581_gpio22_pins[] = { 35 };
++static const int en7581_gpio23_pins[] = { 36 };
++static const int en7581_gpio24_pins[] = { 37 };
++static const int en7581_gpio25_pins[] = { 38 };
++static const int en7581_gpio26_pins[] = { 39 };
++static const int en7581_gpio27_pins[] = { 40 };
++static const int en7581_gpio28_pins[] = { 41 };
++static const int en7581_gpio29_pins[] = { 42 };
++static const int en7581_gpio30_pins[] = { 43 };
++static const int en7581_gpio31_pins[] = { 44 };
++static const int en7581_gpio32_pins[] = { 45 };
++static const int en7581_gpio33_pins[] = { 46 };
++static const int en7581_gpio34_pins[] = { 47 };
++static const int en7581_gpio35_pins[] = { 48 };
++static const int en7581_gpio36_pins[] = { 49 };
++static const int en7581_gpio37_pins[] = { 50 };
++static const int en7581_gpio38_pins[] = { 51 };
++static const int en7581_gpio39_pins[] = { 52 };
++static const int en7581_gpio40_pins[] = { 53 };
++static const int en7581_gpio41_pins[] = { 54 };
++static const int en7581_gpio42_pins[] = { 55 };
++static const int en7581_gpio43_pins[] = { 56 };
++static const int en7581_gpio44_pins[] = { 57 };
++static const int en7581_gpio45_pins[] = { 58 };
++static const int en7581_gpio46_pins[] = { 59 };
++static const int en7581_gpio47_pins[] = { 60 };
++static const int en7581_gpio48_pins[] = { 61 };
++static const int en7581_gpio49_pins[] = { 62 };
++static const int en7581_pcie_reset0_pins[] = { 60 };
++static const int en7581_pcie_reset1_pins[] = { 61 };
++static const int en7581_pcie_reset2_pins[] = { 62 };
++
++static const struct pingroup en7581_pinctrl_groups[] = {
++      PINCTRL_PIN_GROUP("pon", en7581_pon),
++      PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
++      PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
++      PINCTRL_PIN_GROUP("sipo", en7581_sipo),
++      PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
++      PINCTRL_PIN_GROUP("mdio", en7581_mdio),
++      PINCTRL_PIN_GROUP("uart2", en7581_uart2),
++      PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
++      PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
++      PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
++      PINCTRL_PIN_GROUP("uart4", en7581_uart4),
++      PINCTRL_PIN_GROUP("uart5", en7581_uart5),
++      PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
++      PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
++      PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
++      PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
++      PINCTRL_PIN_GROUP("i2s", en7581_i2s),
++      PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
++      PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
++      PINCTRL_PIN_GROUP("spi", en7581_spi),
++      PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
++      PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
++      PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
++      PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
++      PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
++      PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
++      PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
++      PINCTRL_PIN_GROUP("emmc", en7581_emmc),
++      PINCTRL_PIN_GROUP("pnand", en7581_pnand),
++      PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
++      PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
++      PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
++      PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
++      PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
++      PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
++      PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
++      PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
++      PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
++      PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
++      PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
++      PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
++      PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
++      PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
++      PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
++      PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
++      PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
++      PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
++      PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
++      PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
++      PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
++      PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
++      PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
++      PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
++      PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
++      PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
++      PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
++      PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
++      PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
++      PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
++      PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
++      PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
++      PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
++      PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
++      PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
++      PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
++      PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
++      PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
++      PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
++      PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
++      PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
++      PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
++      PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
++      PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
++      PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
++      PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
++      PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
++      PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
++      PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
++      PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
++      PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
++      PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
++      PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
++};
++
++static const char *const pon_groups[] = { "pon" };
++static const char *const tod_1pps_groups[] = {
++      "pon_tod_1pps", "gsw_tod_1pps"
++};
++static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
++static const char *const mdio_groups[] = { "mdio" };
++static const char *const uart_groups[] = {
++      "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
++      "uart4", "uart5"
++};
++static const char *const i2c_groups[] = { "i2c1" };
++static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
++static const char *const pcm_groups[] = { "pcm1", "pcm2" };
++static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
++static const char *const pcm_spi_groups[] = {
++      "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
++      "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3",
++      "pcm_spi_cs4"
++};
++static const char *const i2s_groups[] = { "i2s" };
++static const char *const emmc_groups[] = { "emmc" };
++static const char *const pnand_groups[] = { "pnand" };
++static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
++static const char *const pcie_reset_groups[] = {
++      "pcie_reset0", "pcie_reset1", "pcie_reset2"
++};
++static const char *const pwm_groups[] = {
++      "gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
++      "gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
++      "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
++      "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
++      "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
++      "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
++      "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
++      "gpio46", "gpio47", "gpio48", "gpio49"
++};
++static const char *const phy1_led0_groups[] = {
++      "gpio33", "gpio34", "gpio35", "gpio42"
++};
++static const char *const phy2_led0_groups[] = {
++      "gpio33", "gpio34", "gpio35", "gpio42"
++};
++static const char *const phy3_led0_groups[] = {
++      "gpio33", "gpio34", "gpio35", "gpio42"
++};
++static const char *const phy4_led0_groups[] = {
++      "gpio33", "gpio34", "gpio35", "gpio42"
++};
++static const char *const phy1_led1_groups[] = {
++      "gpio43", "gpio44", "gpio45", "gpio46"
++};
++static const char *const phy2_led1_groups[] = {
++      "gpio43", "gpio44", "gpio45", "gpio46"
++};
++static const char *const phy3_led1_groups[] = {
++      "gpio43", "gpio44", "gpio45", "gpio46"
++};
++static const char *const phy4_led1_groups[] = {
++      "gpio43", "gpio44", "gpio45", "gpio46"
++};
++
++static const struct airoha_pinctrl_func_group pon_func_group[] = {
++      {
++              .name = "pon",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PON_MODE_MASK,
++                      GPIO_PON_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
++      {
++              .name = "pon_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      PON_TOD_1PPS_MODE_MASK,
++                      PON_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "gsw_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GSW_TOD_1PPS_MODE_MASK,
++                      GSW_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group sipo_func_group[] = {
++      {
++              .name = "sipo",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "sipo_rclk",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group mdio_func_group[] = {
++      {
++              .name = "mdio",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GPIO_MDC_IO_MASTER_MODE_MASK,
++                      GPIO_MDC_IO_MASTER_MODE_MASK
++              },
++              .regmap[1] = {
++                      AIROHA_FUNC_MUX,
++                      REG_FORCE_GPIO_EN,
++                      FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2),
++                      FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2)
++              },
++              .regmap_size = 2,
++      },
++};
++
++static const struct airoha_pinctrl_func_group uart_func_group[] = {
++      {
++              .name = "uart2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART2_MODE_MASK,
++                      GPIO_UART2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart2_cts_rts",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
++                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "hsuart",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
++                      GPIO_HSUART_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++      {
++              .name = "hsuart_cts_rts",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART4_MODE_MASK,
++                      GPIO_UART4_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart5",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART5_MODE_MASK,
++                      GPIO_UART5_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group i2c_func_group[] = {
++      {
++              .name = "i2c1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE,
++                      GPIO_2ND_I2C_MODE_MASK | GPIO_I2C_MASTER_MODE_MODE
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group jtag_func_group[] = {
++      {
++              .name = "jtag_udi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_UDI_EN_MASK,
++                      JTAG_UDI_EN_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "jtag_dfd",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_DFD_EN_MASK,
++                      JTAG_DFD_EN_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pcm_func_group[] = {
++      {
++              .name = "pcm1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM1_MODE_MASK,
++                      GPIO_PCM1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM2_MODE_MASK,
++                      GPIO_PCM2_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group spi_func_group[] = {
++      {
++              .name = "spi_quad",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_QUAD_MODE_MASK,
++                      GPIO_SPI_QUAD_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS1_MODE_MASK,
++                      GPIO_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS2_MODE_MASK,
++                      GPIO_SPI_CS2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs3",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS3_MODE_MASK,
++                      GPIO_SPI_CS3_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS4_MODE_MASK,
++                      GPIO_SPI_CS4_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
++      {
++              .name = "pcm_spi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_MODE_MASK,
++                      GPIO_PCM_SPI_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_int",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_INT_MODE_MASK,
++                      GPIO_PCM_INT_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_rst",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_RESET_MODE_MASK,
++                      GPIO_PCM_RESET_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS1_MODE_MASK,
++                      GPIO_PCM_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs2_p128",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS2_MODE_P128_MASK,
++                      GPIO_PCM_SPI_CS2_MODE_P128_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs2_p156",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS2_MODE_P156_MASK,
++                      GPIO_PCM_SPI_CS2_MODE_P156_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs3",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS3_MODE_MASK,
++                      GPIO_PCM_SPI_CS3_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS4_MODE_MASK,
++                      GPIO_PCM_SPI_CS4_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group i2s_func_group[] = {
++      {
++              .name = "i2s",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GPIO_I2S_MODE_MASK,
++                      GPIO_I2S_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group emmc_func_group[] = {
++      {
++              .name = "emmc",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_EMMC_MODE_MASK,
++                      GPIO_EMMC_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pnand_func_group[] = {
++      {
++              .name = "pnand",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PARALLEL_NAND_MODE_MASK,
++                      GPIO_PARALLEL_NAND_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group gpio_func_group[] = {
++      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET2_MASK),
++};
++
++static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
++      {
++              .name = "pcie_reset0",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET0_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcie_reset1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET1_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcie_reset2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET2_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pwm_func_group[] = {
++      AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET2_MASK),
++};
++
++static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
++      PINCTRL_FUNC_DESC("pon", pon),
++      PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
++      PINCTRL_FUNC_DESC("sipo", sipo),
++      PINCTRL_FUNC_DESC("mdio", mdio),
++      PINCTRL_FUNC_DESC("uart", uart),
++      PINCTRL_FUNC_DESC("i2c", i2c),
++      PINCTRL_FUNC_DESC("jtag", jtag),
++      PINCTRL_FUNC_DESC("pcm", pcm),
++      PINCTRL_FUNC_DESC("spi", spi),
++      PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
++      PINCTRL_FUNC_DESC("i2s", i2s),
++      PINCTRL_FUNC_DESC("emmc", emmc),
++      PINCTRL_FUNC_DESC("pnand", pnand),
++      PINCTRL_FUNC_DESC("gpio", gpio),
++      PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
++      PINCTRL_FUNC_DESC("pwm", pwm),
++      PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
++      PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
++      PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
++      PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
++      PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
++      PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
++      PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
++      PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
++};
++
++static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
++      PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
++      PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)),
++      PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)),
++      PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)),
++      PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)),
++      PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)),
++      PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)),
++      PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)),
++      PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)),
++      PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)),
++      PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)),
++      PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)),
++      PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)),
++      PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)),
++      PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)),
++      PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)),
++      PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)),
++      PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)),
++      PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
++      PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
++      PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
++};
++
++static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
++      PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
++      PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)),
++      PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)),
++      PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)),
++      PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)),
++      PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)),
++      PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)),
++      PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)),
++      PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)),
++      PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)),
++      PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)),
++      PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)),
++      PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)),
++      PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)),
++      PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)),
++      PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)),
++      PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)),
++      PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)),
++      PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
++      PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
++      PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
++};
++
++static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
++      PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
++      PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)),
++      PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)),
++      PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)),
++      PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)),
++      PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)),
++      PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)),
++      PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)),
++      PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)),
++      PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)),
++      PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)),
++      PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)),
++      PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)),
++      PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)),
++      PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)),
++      PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)),
++      PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)),
++      PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)),
++      PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
++      PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
++      PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
++};
++
++static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
++      PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
++      PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)),
++      PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)),
++      PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)),
++      PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)),
++      PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)),
++      PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)),
++      PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)),
++      PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)),
++      PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)),
++      PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)),
++      PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)),
++      PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)),
++      PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)),
++      PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)),
++      PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)),
++      PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)),
++      PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)),
++      PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
++      PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
++      PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
++      PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
++};
++
++static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
++      PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
++};
++
++static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
++      .pinctrl_name = KBUILD_MODNAME,
++      .pinctrl_owner = THIS_MODULE,
++      .pins = en7581_pinctrl_pins,
++      .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
++      .grps = en7581_pinctrl_groups,
++      .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
++      .funcs = en7581_pinctrl_funcs,
++      .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
++      .confs_info = {
++              [AIROHA_PINCTRL_CONFS_PULLUP] = {
++                      .confs = en7581_pinctrl_pullup_conf,
++                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
++                      .confs = en7581_pinctrl_pulldown_conf,
++                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
++                      .confs = en7581_pinctrl_drive_e2_conf,
++                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
++                      .confs = en7581_pinctrl_drive_e4_conf,
++                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
++                      .confs = en7581_pinctrl_pcie_rst_od_conf,
++                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
++              },
++      },
++};
++
++static const struct of_device_id airoha_pinctrl_of_match[] = {
++      { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
++
++static struct platform_driver airoha_pinctrl_driver = {
++      .probe = airoha_pinctrl_probe,
++      .driver = {
++              .name = "pinctrl-airoha-an7581",
++              .of_match_table = airoha_pinctrl_of_match,
++      },
++};
++module_platform_driver(airoha_pinctrl_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
++MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
++MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
++MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7581 SoC");
+--- /dev/null
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -0,0 +1,1476 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
++ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
++ * Author: Markus Gothe <markus.gothe@genexis.eu>
++ */
++
++#include "airoha-common.h"
++
++/* MUX */
++#define REG_GPIO_2ND_I2C_MODE                 0x0214
++#define GPIO_LAN3_LED1_MODE_MASK              BIT(10)
++#define GPIO_LAN3_LED0_MODE_MASK              BIT(9)
++#define GPIO_LAN2_LED1_MODE_MASK              BIT(8)
++#define GPIO_LAN2_LED0_MODE_MASK              BIT(7)
++#define GPIO_LAN1_LED1_MODE_MASK              BIT(6)
++#define GPIO_LAN1_LED0_MODE_MASK              BIT(5)
++#define GPIO_LAN0_LED1_MODE_MASK              BIT(4)
++#define GPIO_LAN0_LED0_MODE_MASK              BIT(3)
++#define PON_TOD_1PPS_MODE_MASK                        BIT(2)
++#define GSW_TOD_1PPS_MODE_MASK                        BIT(1)
++
++#define REG_GPIO_SPI_CS1_MODE                 0x0218
++#define GPIO_MDC_IO_MASTER_MODE_MASK          BIT(22)
++#define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
++#define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
++#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK     BIT(18)
++#define GPIO_PCM_SPI_CS1_MODE_MASK            BIT(17)
++#define GPIO_PCM_SPI_MODE_MASK                        BIT(16)
++#define GPIO_PCM2_MODE_MASK                   BIT(13)
++#define GPIO_PCM1_MODE_MASK                   BIT(12)
++#define GPIO_PCM_INT_MODE_MASK                        BIT(9)
++#define GPIO_PCM_RESET_MODE_MASK              BIT(8)
++#define GPIO_SPI_QUAD_MODE_MASK                       BIT(4)
++#define GPIO_SPI_CS4_MODE_MASK                        BIT(3)
++#define GPIO_SPI_CS3_MODE_MASK                        BIT(2)
++#define GPIO_SPI_CS2_MODE_MASK                        BIT(1)
++#define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
++
++#define REG_GPIO_PON_MODE                     0x021c
++#define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
++#define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
++#define AN7583_UART_RXD_GPIO_MODE_MASK                BIT(24)
++#define AN7583_UART_TXD_GPIO_MODE_MASK                BIT(23)
++#define AN7583_SPI_MISO_GPIO_MODE_MASK                BIT(22)
++#define AN7583_SPI_MOSI_GPIO_MODE_MASK                BIT(21)
++#define AN7583_SPI_CS_GPIO_MODE_MASK          BIT(20)
++#define AN7583_SPI_CLK_GPIO_MODE_MASK         BIT(19)
++#define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
++#define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
++#define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
++#define AN7583_I2C0_SCL_GPIO_MODE_MASK                BIT(15)
++#define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
++#define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
++#define SIPO_RCLK_MODE_MASK                   BIT(11)
++#define GPIO_PCIE_RESET1_MASK                 BIT(10)
++#define GPIO_PCIE_RESET0_MASK                 BIT(9)
++#define GPIO_UART5_MODE_MASK                  BIT(8)
++#define GPIO_UART4_MODE_MASK                  BIT(7)
++#define GPIO_HSUART_CTS_RTS_MODE_MASK         BIT(6)
++#define GPIO_HSUART_MODE_MASK                 BIT(5)
++#define GPIO_UART2_CTS_RTS_MODE_MASK          BIT(4)
++#define GPIO_UART2_MODE_MASK                  BIT(3)
++#define GPIO_SIPO_MODE_MASK                   BIT(2)
++#define GPIO_EMMC_MODE_MASK                   BIT(1)
++#define GPIO_PON_MODE_MASK                    BIT(0)
++
++#define REG_NPU_UART_EN                               0x0224
++#define JTAG_UDI_EN_MASK                      BIT(4)
++#define JTAG_DFD_EN_MASK                      BIT(3)
++
++#define REG_FORCE_GPIO_EN                     0x0228
++#define FORCE_GPIO_EN(n)                      BIT(n)
++
++/* LED MAP */
++#define REG_LAN_LED0_MAPPING                  0x027c
++#define REG_LAN_LED1_MAPPING                  0x0280
++
++#define LAN4_LED_MAPPING_MASK                 GENMASK(18, 16)
++#define LAN4_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n))
++
++#define LAN3_LED_MAPPING_MASK                 GENMASK(14, 12)
++#define LAN3_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
++
++#define LAN2_LED_MAPPING_MASK                 GENMASK(10, 8)
++#define LAN2_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
++
++#define LAN1_LED_MAPPING_MASK                 GENMASK(6, 4)
++#define LAN1_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
++
++#define LAN0_LED_MAPPING_MASK                 GENMASK(2, 0)
++#define LAN0_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
++
++/* CONF */
++#define REG_I2C_SDA_E2                                0x001c
++#define AN7583_I2C1_SCL_E2_MASK                       BIT(16)
++#define AN7583_I2C1_SDA_E2_MASK                       BIT(15)
++#define SPI_MISO_E2_MASK                      BIT(14)
++#define SPI_MOSI_E2_MASK                      BIT(13)
++#define SPI_CLK_E2_MASK                               BIT(12)
++#define SPI_CS0_E2_MASK                               BIT(11)
++#define PCIE1_RESET_E2_MASK                   BIT(9)
++#define PCIE0_RESET_E2_MASK                   BIT(8)
++#define AN7583_MDIO_0_E2_MASK                 BIT(5)
++#define AN7583_MDC_0_E2_MASK                  BIT(4)
++#define UART1_RXD_E2_MASK                     BIT(3)
++#define UART1_TXD_E2_MASK                     BIT(2)
++#define I2C_SCL_E2_MASK                               BIT(1)
++#define I2C_SDA_E2_MASK                               BIT(0)
++
++#define REG_I2C_SDA_E4                                0x0020
++#define AN7583_I2C1_SCL_E4_MASK                       BIT(16)
++#define AN7583_I2C1_SDA_E4_MASK                       BIT(15)
++#define SPI_MISO_E4_MASK                      BIT(14)
++#define SPI_MOSI_E4_MASK                      BIT(13)
++#define SPI_CLK_E4_MASK                               BIT(12)
++#define SPI_CS0_E4_MASK                               BIT(11)
++#define PCIE1_RESET_E4_MASK                   BIT(9)
++#define PCIE0_RESET_E4_MASK                   BIT(8)
++#define AN7583_MDIO_0_E4_MASK                 BIT(5)
++#define AN7583_MDC_0_E4_MASK                  BIT(4)
++#define UART1_RXD_E4_MASK                     BIT(3)
++#define UART1_TXD_E4_MASK                     BIT(2)
++#define I2C_SCL_E4_MASK                               BIT(1)
++#define I2C_SDA_E4_MASK                               BIT(0)
++
++#define REG_GPIO_L_E2                         0x0024
++#define REG_GPIO_L_E4                         0x0028
++#define REG_GPIO_H_E2                         0x002c
++#define REG_GPIO_H_E4                         0x0030
++
++#define REG_I2C_SDA_PU                                0x0044
++#define AN7583_I2C1_SCL_PU_MASK                       BIT(16)
++#define AN7583_I2C1_SDA_PU_MASK                       BIT(15)
++#define SPI_MISO_PU_MASK                      BIT(14)
++#define SPI_MOSI_PU_MASK                      BIT(13)
++#define SPI_CLK_PU_MASK                               BIT(12)
++#define SPI_CS0_PU_MASK                               BIT(11)
++#define PCIE1_RESET_PU_MASK                   BIT(9)
++#define PCIE0_RESET_PU_MASK                   BIT(8)
++#define AN7583_MDIO_0_PU_MASK                 BIT(5)
++#define AN7583_MDC_0_PU_MASK                  BIT(4)
++#define UART1_RXD_PU_MASK                     BIT(3)
++#define UART1_TXD_PU_MASK                     BIT(2)
++#define I2C_SCL_PU_MASK                               BIT(1)
++#define I2C_SDA_PU_MASK                               BIT(0)
++
++#define REG_I2C_SDA_PD                                0x0048
++#define AN7583_I2C1_SCL_PD_MASK                       BIT(16)
++#define AN7583_I2C1_SDA_PD_MASK                       BIT(15)
++#define SPI_MISO_PD_MASK                      BIT(14)
++#define SPI_MOSI_PD_MASK                      BIT(13)
++#define SPI_CLK_PD_MASK                               BIT(12)
++#define SPI_CS0_PD_MASK                               BIT(11)
++#define PCIE1_RESET_PD_MASK                   BIT(9)
++#define PCIE0_RESET_PD_MASK                   BIT(8)
++#define AN7583_MDIO_0_PD_MASK                 BIT(5)
++#define AN7583_MDC_0_PD_MASK                  BIT(4)
++#define UART1_RXD_PD_MASK                     BIT(3)
++#define UART1_TXD_PD_MASK                     BIT(2)
++#define I2C_SCL_PD_MASK                               BIT(1)
++#define I2C_SDA_PD_MASK                               BIT(0)
++
++#define REG_GPIO_L_PU                         0x004c
++#define REG_GPIO_L_PD                         0x0050
++#define REG_GPIO_H_PU                         0x0054
++#define REG_GPIO_H_PD                         0x0058
++
++#define REG_PCIE_RESET_OD                     0x018c
++#define PCIE1_RESET_OD_MASK                   BIT(1)
++#define PCIE0_RESET_OD_MASK                   BIT(0)
++
++/* PWM MODE CONF */
++#define REG_GPIO_FLASH_MODE_CFG                       0x0034
++#define GPIO15_FLASH_MODE_CFG                 BIT(15)
++#define GPIO14_FLASH_MODE_CFG                 BIT(14)
++#define GPIO13_FLASH_MODE_CFG                 BIT(13)
++#define GPIO12_FLASH_MODE_CFG                 BIT(12)
++#define GPIO11_FLASH_MODE_CFG                 BIT(11)
++#define GPIO10_FLASH_MODE_CFG                 BIT(10)
++#define GPIO9_FLASH_MODE_CFG                  BIT(9)
++#define GPIO8_FLASH_MODE_CFG                  BIT(8)
++#define GPIO7_FLASH_MODE_CFG                  BIT(7)
++#define GPIO6_FLASH_MODE_CFG                  BIT(6)
++#define GPIO5_FLASH_MODE_CFG                  BIT(5)
++#define GPIO4_FLASH_MODE_CFG                  BIT(4)
++#define GPIO3_FLASH_MODE_CFG                  BIT(3)
++#define GPIO2_FLASH_MODE_CFG                  BIT(2)
++#define GPIO1_FLASH_MODE_CFG                  BIT(1)
++#define GPIO0_FLASH_MODE_CFG                  BIT(0)
++
++/* PWM MODE CONF EXT */
++#define REG_GPIO_FLASH_MODE_CFG_EXT           0x0068
++#define GPIO51_FLASH_MODE_CFG                 BIT(31)
++#define GPIO50_FLASH_MODE_CFG                 BIT(30)
++#define GPIO49_FLASH_MODE_CFG                 BIT(29)
++#define GPIO48_FLASH_MODE_CFG                 BIT(28)
++#define GPIO47_FLASH_MODE_CFG                 BIT(27)
++#define GPIO46_FLASH_MODE_CFG                 BIT(26)
++#define GPIO45_FLASH_MODE_CFG                 BIT(25)
++#define GPIO44_FLASH_MODE_CFG                 BIT(24)
++#define GPIO43_FLASH_MODE_CFG                 BIT(23)
++#define GPIO42_FLASH_MODE_CFG                 BIT(22)
++#define GPIO41_FLASH_MODE_CFG                 BIT(21)
++#define GPIO40_FLASH_MODE_CFG                 BIT(20)
++#define GPIO39_FLASH_MODE_CFG                 BIT(19)
++#define GPIO38_FLASH_MODE_CFG                 BIT(18)
++#define GPIO37_FLASH_MODE_CFG                 BIT(17)
++#define GPIO36_FLASH_MODE_CFG                 BIT(16)
++#define GPIO31_FLASH_MODE_CFG                 BIT(15)
++#define GPIO30_FLASH_MODE_CFG                 BIT(14)
++#define GPIO29_FLASH_MODE_CFG                 BIT(13)
++#define GPIO28_FLASH_MODE_CFG                 BIT(12)
++#define GPIO27_FLASH_MODE_CFG                 BIT(11)
++#define GPIO26_FLASH_MODE_CFG                 BIT(10)
++#define GPIO25_FLASH_MODE_CFG                 BIT(9)
++#define GPIO24_FLASH_MODE_CFG                 BIT(8)
++#define GPIO23_FLASH_MODE_CFG                 BIT(7)
++#define GPIO22_FLASH_MODE_CFG                 BIT(6)
++#define GPIO21_FLASH_MODE_CFG                 BIT(5)
++#define GPIO20_FLASH_MODE_CFG                 BIT(4)
++#define GPIO19_FLASH_MODE_CFG                 BIT(3)
++#define GPIO18_FLASH_MODE_CFG                 BIT(2)
++#define GPIO17_FLASH_MODE_CFG                 BIT(1)
++#define GPIO16_FLASH_MODE_CFG                 BIT(0)
++
++#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      0                                       \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++/* PWM */
++#define AIROHA_PINCTRL_PWM(gpio, mux_val)                     \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_MUX,                    \
++                      REG_GPIO_FLASH_MODE_CFG,                \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)                 \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED0_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED1_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
++      PINCTRL_PIN(2, "gpio0"),
++      PINCTRL_PIN(3, "gpio1"),
++      PINCTRL_PIN(4, "gpio2"),
++      PINCTRL_PIN(5, "gpio3"),
++      PINCTRL_PIN(6, "gpio4"),
++      PINCTRL_PIN(7, "gpio5"),
++      PINCTRL_PIN(8, "gpio6"),
++      PINCTRL_PIN(9, "gpio7"),
++      PINCTRL_PIN(10, "gpio8"),
++      PINCTRL_PIN(11, "gpio9"),
++      PINCTRL_PIN(12, "gpio10"),
++      PINCTRL_PIN(13, "gpio11"),
++      PINCTRL_PIN(14, "gpio12"),
++      PINCTRL_PIN(15, "gpio13"),
++      PINCTRL_PIN(16, "gpio14"),
++      PINCTRL_PIN(17, "gpio15"),
++      PINCTRL_PIN(18, "gpio16"),
++      PINCTRL_PIN(19, "gpio17"),
++      PINCTRL_PIN(20, "gpio18"),
++      PINCTRL_PIN(21, "gpio19"),
++      PINCTRL_PIN(22, "gpio20"),
++      PINCTRL_PIN(23, "gpio21"),
++      PINCTRL_PIN(24, "gpio22"),
++      PINCTRL_PIN(25, "gpio23"),
++      PINCTRL_PIN(26, "gpio24"),
++      PINCTRL_PIN(27, "gpio25"),
++      PINCTRL_PIN(28, "gpio26"),
++      PINCTRL_PIN(29, "gpio27"),
++      PINCTRL_PIN(30, "gpio28"),
++      PINCTRL_PIN(31, "gpio29"),
++      PINCTRL_PIN(32, "gpio30"),
++      PINCTRL_PIN(33, "gpio31"),
++      PINCTRL_PIN(34, "gpio32"),
++      PINCTRL_PIN(35, "gpio33"),
++      PINCTRL_PIN(36, "gpio34"),
++      PINCTRL_PIN(37, "gpio35"),
++      PINCTRL_PIN(38, "gpio36"),
++      PINCTRL_PIN(39, "gpio37"),
++      PINCTRL_PIN(40, "gpio38"),
++      PINCTRL_PIN(41, "i2c0_scl"),
++      PINCTRL_PIN(42, "i2c0_sda"),
++      PINCTRL_PIN(43, "i2c1_scl"),
++      PINCTRL_PIN(44, "i2c1_sda"),
++      PINCTRL_PIN(45, "spi_clk"),
++      PINCTRL_PIN(46, "spi_cs"),
++      PINCTRL_PIN(47, "spi_mosi"),
++      PINCTRL_PIN(48, "spi_miso"),
++      PINCTRL_PIN(49, "uart_txd"),
++      PINCTRL_PIN(50, "uart_rxd"),
++      PINCTRL_PIN(51, "pcie_reset0"),
++      PINCTRL_PIN(52, "pcie_reset1"),
++      PINCTRL_PIN(53, "mdc_0"),
++      PINCTRL_PIN(54, "mdio_0"),
++};
++
++static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
++static const int an7583_pon_tod_1pps_pins[] = { 32 };
++static const int an7583_gsw_tod_1pps_pins[] = { 32 };
++static const int an7583_sipo_pins[] = { 34, 35 };
++static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
++static const int an7583_mdio_pins[] = { 53, 54 };
++static const int an7583_mdio1_pins[] = { 43, 44 };
++static const int an7583_uart2_pins[] = { 34, 35 };
++static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
++static const int an7583_hsuart_pins[] = { 30, 31 };
++static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
++static const int an7583_npu_uart_pins[] = { 7, 8 };
++static const int an7583_uart4_pins[] = { 7, 8 };
++static const int an7583_uart5_pins[] = { 23, 24 };
++static const int an7583_i2c0_pins[] = { 41, 42 };
++static const int an7583_i2c1_pins[] = { 43, 44 };
++static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
++static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
++static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
++static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
++static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
++static const int an7583_spi_quad_pins[] = { 25, 26 };
++static const int an7583_spi_cs1_pins[] = { 27 };
++static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
++static const int an7583_pcm_spi_rst_pins[] = { 14 };
++static const int an7583_pcm_spi_cs1_pins[] = { 24 };
++static const int an7583_emmc_pins[] = {
++      7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
++};
++static const int an7583_pnand_pins[] = {
++      7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
++};
++static const int an7583_gpio0_pins[] = { 2 };
++static const int an7583_gpio1_pins[] = { 3 };
++static const int an7583_gpio2_pins[] = { 4 };
++static const int an7583_gpio3_pins[] = { 5 };
++static const int an7583_gpio4_pins[] = { 6 };
++static const int an7583_gpio5_pins[] = { 7 };
++static const int an7583_gpio6_pins[] = { 8 };
++static const int an7583_gpio7_pins[] = { 9 };
++static const int an7583_gpio8_pins[] = { 10 };
++static const int an7583_gpio9_pins[] = { 11 };
++static const int an7583_gpio10_pins[] = { 12 };
++static const int an7583_gpio11_pins[] = { 13 };
++static const int an7583_gpio12_pins[] = { 14 };
++static const int an7583_gpio13_pins[] = { 15 };
++static const int an7583_gpio14_pins[] = { 16 };
++static const int an7583_gpio15_pins[] = { 17 };
++static const int an7583_gpio16_pins[] = { 18 };
++static const int an7583_gpio17_pins[] = { 19 };
++static const int an7583_gpio18_pins[] = { 20 };
++static const int an7583_gpio19_pins[] = { 21 };
++static const int an7583_gpio20_pins[] = { 22 };
++static const int an7583_gpio21_pins[] = { 23 };
++static const int an7583_gpio22_pins[] = { 24 };
++static const int an7583_gpio23_pins[] = { 25 };
++static const int an7583_gpio24_pins[] = { 26 };
++static const int an7583_gpio25_pins[] = { 27 };
++static const int an7583_gpio26_pins[] = { 28 };
++static const int an7583_gpio27_pins[] = { 29 };
++static const int an7583_gpio28_pins[] = { 30 };
++static const int an7583_gpio29_pins[] = { 31 };
++static const int an7583_gpio30_pins[] = { 32 };
++static const int an7583_gpio31_pins[] = { 33 };
++static const int an7583_gpio32_pins[] = { 34 };
++static const int an7583_gpio33_pins[] = { 35 };
++static const int an7583_gpio34_pins[] = { 36 };
++static const int an7583_gpio35_pins[] = { 37 };
++static const int an7583_gpio36_pins[] = { 38 };
++static const int an7583_gpio37_pins[] = { 39 };
++static const int an7583_gpio38_pins[] = { 40 };
++static const int an7583_gpio39_pins[] = { 41 };
++static const int an7583_gpio40_pins[] = { 42 };
++static const int an7583_gpio41_pins[] = { 43 };
++static const int an7583_gpio42_pins[] = { 44 };
++static const int an7583_gpio43_pins[] = { 45 };
++static const int an7583_gpio44_pins[] = { 46 };
++static const int an7583_gpio45_pins[] = { 47 };
++static const int an7583_gpio46_pins[] = { 48 };
++static const int an7583_gpio47_pins[] = { 49 };
++static const int an7583_gpio48_pins[] = { 50 };
++static const int an7583_gpio49_pins[] = { 51 };
++static const int an7583_gpio50_pins[] = { 52 };
++static const int an7583_gpio51_pins[] = { 53 };
++static const int an7583_gpio52_pins[] = { 54 };
++static const int an7583_pcie_reset0_pins[] = { 51 };
++static const int an7583_pcie_reset1_pins[] = { 52 };
++
++static const struct pingroup an7583_pinctrl_groups[] = {
++      PINCTRL_PIN_GROUP("pon", an7583_pon),
++      PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
++      PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
++      PINCTRL_PIN_GROUP("sipo", an7583_sipo),
++      PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
++      PINCTRL_PIN_GROUP("mdio", an7583_mdio),
++      PINCTRL_PIN_GROUP("mdio1", an7583_mdio1),
++      PINCTRL_PIN_GROUP("uart2", an7583_uart2),
++      PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
++      PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
++      PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
++      PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
++      PINCTRL_PIN_GROUP("uart4", an7583_uart4),
++      PINCTRL_PIN_GROUP("uart5", an7583_uart5),
++      PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
++      PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
++      PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
++      PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
++      PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
++      PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
++      PINCTRL_PIN_GROUP("spi", an7583_spi),
++      PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
++      PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
++      PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
++      PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
++      PINCTRL_PIN_GROUP("emmc", an7583_emmc),
++      PINCTRL_PIN_GROUP("pnand", an7583_pnand),
++      PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
++      PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
++      PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
++      PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
++      PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
++      PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
++      PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
++      PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
++      PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
++      PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
++      PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
++      PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
++      PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
++      PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
++      PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
++      PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
++      PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
++      PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
++      PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
++      PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
++      PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
++      PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
++      PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
++      PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
++      PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
++      PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
++      PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
++      PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
++      PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
++      PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
++      PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
++      PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
++      PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
++      PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
++      PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
++      PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
++      PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
++      PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
++      PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
++      PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
++      PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
++      PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
++      PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
++      PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
++      PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
++      PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
++      PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
++      PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
++      PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
++      PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
++      PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
++      PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
++      PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
++      PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
++      PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
++};
++
++static const char *const pon_groups[] = { "pon" };
++static const char *const tod_1pps_groups[] = {
++      "pon_tod_1pps", "gsw_tod_1pps"
++};
++static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
++static const char *const an7583_mdio_groups[] = { "mdio" };
++static const char *const uart_groups[] = {
++      "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
++      "uart4", "uart5"
++};
++static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" };
++static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
++static const char *const pcm_groups[] = { "pcm1", "pcm2" };
++static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
++static const char *const an7583_pcm_spi_groups[] = {
++      "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
++};
++static const char *const emmc_groups[] = { "emmc" };
++static const char *const pnand_groups[] = { "pnand" };
++static const char *const an7583_gpio_groups[] = {
++      "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
++      "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
++      "gpio49", "gpio50", "gpio51", "gpio52"
++};
++static const char *const an7583_pcie_reset_groups[] = {
++      "pcie_reset0", "pcie_reset1"
++};
++static const char *const an7583_pwm_groups[] = {
++      "gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
++      "gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
++      "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
++      "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
++      "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
++      "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39",
++      "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
++      "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
++};
++static const char *const an7583_phy1_led0_groups[] = {
++      "gpio1", "gpio2", "gpio3", "gpio4"
++};
++static const char *const an7583_phy2_led0_groups[] = {
++      "gpio1", "gpio2", "gpio3", "gpio4"
++};
++static const char *const an7583_phy3_led0_groups[] = {
++      "gpio1", "gpio2", "gpio3", "gpio4"
++};
++static const char *const an7583_phy4_led0_groups[] = {
++      "gpio1", "gpio2", "gpio3", "gpio4"
++};
++static const char *const an7583_phy1_led1_groups[] = {
++      "gpio8", "gpio9", "gpio10", "gpio11"
++};
++static const char *const an7583_phy2_led1_groups[] = {
++      "gpio8", "gpio9", "gpio10", "gpio11"
++};
++static const char *const an7583_phy3_led1_groups[] = {
++      "gpio8", "gpio9", "gpio10", "gpio11"
++};
++static const char *const an7583_phy4_led1_groups[] = {
++      "gpio8", "gpio9", "gpio10", "gpio11"
++};
++
++static const struct airoha_pinctrl_func_group pon_func_group[] = {
++      {
++              .name = "pon",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PON_MODE_MASK,
++                      GPIO_PON_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
++      {
++              .name = "pon_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      PON_TOD_1PPS_MODE_MASK,
++                      PON_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "gsw_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GSW_TOD_1PPS_MODE_MASK,
++                      GSW_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group sipo_func_group[] = {
++      {
++              .name = "sipo",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "sipo_rclk",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
++      {
++              .name = "mdio",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group uart_func_group[] = {
++      {
++              .name = "uart2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART2_MODE_MASK,
++                      GPIO_UART2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart2_cts_rts",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK,
++                      GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "hsuart",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
++                      GPIO_HSUART_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++      {
++              .name = "hsuart_cts_rts",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK,
++                      GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART4_MODE_MASK,
++                      GPIO_UART4_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "uart5",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART5_MODE_MASK,
++                      GPIO_UART5_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = {
++      {
++              .name = "i2c0",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "i2c1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group jtag_func_group[] = {
++      {
++              .name = "jtag_udi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_UDI_EN_MASK,
++                      JTAG_UDI_EN_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "jtag_dfd",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_DFD_EN_MASK,
++                      JTAG_DFD_EN_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pcm_func_group[] = {
++      {
++              .name = "pcm1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM1_MODE_MASK,
++                      GPIO_PCM1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM2_MODE_MASK,
++                      GPIO_PCM2_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group spi_func_group[] = {
++      {
++              .name = "spi_quad",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_QUAD_MODE_MASK,
++                      GPIO_SPI_QUAD_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS1_MODE_MASK,
++                      GPIO_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS2_MODE_MASK,
++                      GPIO_SPI_CS2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs3",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS3_MODE_MASK,
++                      GPIO_SPI_CS3_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS4_MODE_MASK,
++                      GPIO_SPI_CS4_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
++      {
++              .name = "pcm_spi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_MODE_MASK,
++                      GPIO_PCM_SPI_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_int",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_INT_MODE_MASK,
++                      GPIO_PCM_INT_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_rst",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_RESET_MODE_MASK,
++                      GPIO_PCM_RESET_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS1_MODE_MASK,
++                      GPIO_PCM_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
++                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs3",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS3_MODE_MASK,
++                      GPIO_PCM_SPI_CS3_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS4_MODE_MASK,
++                      GPIO_PCM_SPI_CS4_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group emmc_func_group[] = {
++      {
++              .name = "emmc",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_EMMC_MODE_MASK,
++                      GPIO_EMMC_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pnand_func_group[] = {
++      {
++              .name = "pnand",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PARALLEL_NAND_MODE_MASK,
++                      GPIO_PARALLEL_NAND_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
++      AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
++                              AN7583_I2C0_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
++                              AN7583_I2C0_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
++                              AN7583_I2C1_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
++                              AN7583_I2C1_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
++                              AN7583_SPI_CLK_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
++                              AN7583_SPI_CS_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
++                              AN7583_SPI_MOSI_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
++                              AN7583_SPI_MISO_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
++                              AN7583_UART_TXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
++                              AN7583_UART_RXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
++                              AN7583_MDC_0_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
++};
++
++static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
++      {
++              .name = "pcie_reset0",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET0_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcie_reset1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET1_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
++      AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
++                                 AN7583_I2C0_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
++                                 AN7583_I2C0_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
++                                 AN7583_I2C1_SCL_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
++                                 AN7583_I2C1_SDA_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
++                                 AN7583_SPI_CLK_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
++                                 AN7583_SPI_CS_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
++                                 AN7583_SPI_MOSI_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
++                                 AN7583_SPI_MISO_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
++                                 AN7583_UART_TXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
++                                 AN7583_UART_RXD_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET1_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
++                                 AN7583_MDC_0_GPIO_MODE_MASK),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
++      PINCTRL_FUNC_DESC("pon", pon),
++      PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
++      PINCTRL_FUNC_DESC("sipo", sipo),
++      PINCTRL_FUNC_DESC("mdio", an7583_mdio),
++      PINCTRL_FUNC_DESC("uart", uart),
++      PINCTRL_FUNC_DESC("i2c", an7583_i2c),
++      PINCTRL_FUNC_DESC("jtag", jtag),
++      PINCTRL_FUNC_DESC("pcm", pcm),
++      PINCTRL_FUNC_DESC("spi", spi),
++      PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
++      PINCTRL_FUNC_DESC("emmc", emmc),
++      PINCTRL_FUNC_DESC("pnand", pnand),
++      PINCTRL_FUNC_DESC("gpio", an7583_gpio),
++      PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
++      PINCTRL_FUNC_DESC("pwm", an7583_pwm),
++      PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
++      PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
++      PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
++      PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
++      PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
++      PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
++      PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
++      PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
++};
++
++static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
++      PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
++      PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
++      PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)),
++      PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)),
++      PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)),
++      PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)),
++      PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)),
++      PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)),
++      PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
++      PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
++      PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
++      PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
++      PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
++      PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
++      PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
++      PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
++};
++
++static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
++      PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
++      PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
++      PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)),
++      PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)),
++      PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)),
++      PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)),
++      PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)),
++      PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)),
++      PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
++      PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
++      PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
++      PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
++      PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
++      PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
++      PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
++      PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
++};
++
++static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
++      PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
++      PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
++      PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)),
++      PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)),
++      PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)),
++      PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)),
++      PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)),
++      PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)),
++      PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
++      PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
++      PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
++      PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
++      PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
++      PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
++      PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
++      PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
++};
++
++static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
++      PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
++      PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
++      PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)),
++      PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)),
++      PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)),
++      PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)),
++      PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)),
++      PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)),
++      PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)),
++      PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
++      PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
++      PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
++      PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
++      PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
++      PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
++      PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
++      PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
++};
++
++static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
++      PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
++      PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
++};
++
++static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
++      .pinctrl_name = KBUILD_MODNAME,
++      .pinctrl_owner = THIS_MODULE,
++      .pins = an7583_pinctrl_pins,
++      .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
++      .grps = an7583_pinctrl_groups,
++      .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
++      .funcs = an7583_pinctrl_funcs,
++      .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
++      .confs_info = {
++              [AIROHA_PINCTRL_CONFS_PULLUP] = {
++                      .confs = an7583_pinctrl_pullup_conf,
++                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
++                      .confs = an7583_pinctrl_pulldown_conf,
++                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
++                      .confs = an7583_pinctrl_drive_e2_conf,
++                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
++                      .confs = an7583_pinctrl_drive_e4_conf,
++                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
++                      .confs = an7583_pinctrl_pcie_rst_od_conf,
++                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
++              },
++      },
++};
++
++static const struct of_device_id airoha_pinctrl_of_match[] = {
++      { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
++
++static struct platform_driver airoha_pinctrl_driver = {
++      .probe = airoha_pinctrl_probe,
++      .driver = {
++              .name = "pinctrl-airoha-an7583",
++              .of_match_table = airoha_pinctrl_of_match,
++      },
++};
++module_platform_driver(airoha_pinctrl_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
++MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
++MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
++MODULE_DESCRIPTION("Pinctrl driver for Airoha AN7583 SoC");

diff --git a/target/linux/airoha/patches-6.18/202-21-v7.3-pinctrl-airoha-an7581-remove-en7581-prefix-from-.patch b/target/linux/airoha/patches-6.18/202-21-v7.3-pinctrl-airoha-an7581-remove-en7581-prefix-from-.patch
new file mode 100644 (file)
index 0000000..b8f0561
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-21-v7.3-pinctrl-airoha-an7581-remove-en7581-prefix-from-.patch
@@ -0,0 +1,496 @@
+From 323e9f48ab562198f962be2cf3089a68dc590dcb Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Thu, 4 Jun 2026 07:54:24 +0300
+Subject: [PATCH v11 26/37] pinctrl: airoha: an7581: remove en7581 prefix from
+ variable names
+
+We have only an7581 specific code in the pinctrl-an7581 kernel module,
+so 'en7581_' prefix is not necessary anymore. Remove it.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7581.c | 398 ++++++++++++------------
+ 1 file changed, 199 insertions(+), 199 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
+@@ -316,7 +316,7 @@
+               .regmap_size = 2,                                       \
+       }
+ 
+-static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
++static struct pinctrl_pin_desc pinctrl_pins[] = {
+       PINCTRL_PIN(0, "uart1_txd"),
+       PINCTRL_PIN(1, "uart1_rxd"),
+       PINCTRL_PIN(2, "i2c_scl"),
+@@ -377,184 +377,184 @@ static struct pinctrl_pin_desc en7581_pi
+       PINCTRL_PIN(62, "pcie_reset2"),
+ };
+ 
+-static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
+-static const int en7581_pon_tod_1pps_pins[] = { 46 };
+-static const int en7581_gsw_tod_1pps_pins[] = { 46 };
+-static const int en7581_sipo_pins[] = { 16, 17 };
+-static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 };
+-static const int en7581_mdio_pins[] = { 14, 15 };
+-static const int en7581_uart2_pins[] = { 48, 55 };
+-static const int en7581_uart2_cts_rts_pins[] = { 46, 47 };
+-static const int en7581_hsuart_pins[] = { 28, 29 };
+-static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 };
+-static const int en7581_uart4_pins[] = { 38, 39 };
+-static const int en7581_uart5_pins[] = { 18, 19 };
+-static const int en7581_i2c0_pins[] = { 2, 3 };
+-static const int en7581_i2c1_pins[] = { 14, 15 };
+-static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
+-static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
+-static const int en7581_i2s_pins[] = { 26, 27, 28, 29 };
+-static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 };
+-static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 };
+-static const int en7581_spi_quad_pins[] = { 32, 33 };
+-static const int en7581_spi_pins[] = { 4, 5, 6, 7 };
+-static const int en7581_spi_cs1_pins[] = { 34 };
+-static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
+-static const int en7581_pcm_spi_int_pins[] = { 14 };
+-static const int en7581_pcm_spi_rst_pins[] = { 15 };
+-static const int en7581_pcm_spi_cs1_pins[] = { 43 };
+-static const int en7581_pcm_spi_cs2_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 };
+-static const int en7581_pcm_spi_cs3_pins[] = { 41 };
+-static const int en7581_pcm_spi_cs4_pins[] = { 42 };
+-static const int en7581_emmc_pins[] = {
++static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 };
++static const int pon_tod_1pps_pins[] = { 46 };
++static const int gsw_tod_1pps_pins[] = { 46 };
++static const int sipo_pins[] = { 16, 17 };
++static const int sipo_rclk_pins[] = { 16, 17, 43 };
++static const int mdio_pins[] = { 14, 15 };
++static const int uart2_pins[] = { 48, 55 };
++static const int uart2_cts_rts_pins[] = { 46, 47 };
++static const int hsuart_pins[] = { 28, 29 };
++static const int hsuart_cts_rts_pins[] = { 26, 27 };
++static const int uart4_pins[] = { 38, 39 };
++static const int uart5_pins[] = { 18, 19 };
++static const int i2c0_pins[] = { 2, 3 };
++static const int i2c1_pins[] = { 14, 15 };
++static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 };
++static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 };
++static const int i2s_pins[] = { 26, 27, 28, 29 };
++static const int pcm1_pins[] = { 22, 23, 24, 25 };
++static const int pcm2_pins[] = { 18, 19, 20, 21 };
++static const int spi_quad_pins[] = { 32, 33 };
++static const int spi_pins[] = { 4, 5, 6, 7 };
++static const int spi_cs1_pins[] = { 34 };
++static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 };
++static const int pcm_spi_int_pins[] = { 14 };
++static const int pcm_spi_rst_pins[] = { 15 };
++static const int pcm_spi_cs1_pins[] = { 43 };
++static const int pcm_spi_cs2_pins[] = { 40 };
++static const int pcm_spi_cs2_p128_pins[] = { 40 };
++static const int pcm_spi_cs2_p156_pins[] = { 40 };
++static const int pcm_spi_cs3_pins[] = { 41 };
++static const int pcm_spi_cs4_pins[] = { 42 };
++static const int emmc_pins[] = {
+       4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37
+ };
+-static const int en7581_pnand_pins[] = {
++static const int pnand_pins[] = {
+       4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42
+ };
+-static const int en7581_gpio0_pins[] = { 13 };
+-static const int en7581_gpio1_pins[] = { 14 };
+-static const int en7581_gpio2_pins[] = { 15 };
+-static const int en7581_gpio3_pins[] = { 16 };
+-static const int en7581_gpio4_pins[] = { 17 };
+-static const int en7581_gpio5_pins[] = { 18 };
+-static const int en7581_gpio6_pins[] = { 19 };
+-static const int en7581_gpio7_pins[] = { 20 };
+-static const int en7581_gpio8_pins[] = { 21 };
+-static const int en7581_gpio9_pins[] = { 22 };
+-static const int en7581_gpio10_pins[] = { 23 };
+-static const int en7581_gpio11_pins[] = { 24 };
+-static const int en7581_gpio12_pins[] = { 25 };
+-static const int en7581_gpio13_pins[] = { 26 };
+-static const int en7581_gpio14_pins[] = { 27 };
+-static const int en7581_gpio15_pins[] = { 28 };
+-static const int en7581_gpio16_pins[] = { 29 };
+-static const int en7581_gpio17_pins[] = { 30 };
+-static const int en7581_gpio18_pins[] = { 31 };
+-static const int en7581_gpio19_pins[] = { 32 };
+-static const int en7581_gpio20_pins[] = { 33 };
+-static const int en7581_gpio21_pins[] = { 34 };
+-static const int en7581_gpio22_pins[] = { 35 };
+-static const int en7581_gpio23_pins[] = { 36 };
+-static const int en7581_gpio24_pins[] = { 37 };
+-static const int en7581_gpio25_pins[] = { 38 };
+-static const int en7581_gpio26_pins[] = { 39 };
+-static const int en7581_gpio27_pins[] = { 40 };
+-static const int en7581_gpio28_pins[] = { 41 };
+-static const int en7581_gpio29_pins[] = { 42 };
+-static const int en7581_gpio30_pins[] = { 43 };
+-static const int en7581_gpio31_pins[] = { 44 };
+-static const int en7581_gpio32_pins[] = { 45 };
+-static const int en7581_gpio33_pins[] = { 46 };
+-static const int en7581_gpio34_pins[] = { 47 };
+-static const int en7581_gpio35_pins[] = { 48 };
+-static const int en7581_gpio36_pins[] = { 49 };
+-static const int en7581_gpio37_pins[] = { 50 };
+-static const int en7581_gpio38_pins[] = { 51 };
+-static const int en7581_gpio39_pins[] = { 52 };
+-static const int en7581_gpio40_pins[] = { 53 };
+-static const int en7581_gpio41_pins[] = { 54 };
+-static const int en7581_gpio42_pins[] = { 55 };
+-static const int en7581_gpio43_pins[] = { 56 };
+-static const int en7581_gpio44_pins[] = { 57 };
+-static const int en7581_gpio45_pins[] = { 58 };
+-static const int en7581_gpio46_pins[] = { 59 };
+-static const int en7581_gpio47_pins[] = { 60 };
+-static const int en7581_gpio48_pins[] = { 61 };
+-static const int en7581_gpio49_pins[] = { 62 };
+-static const int en7581_pcie_reset0_pins[] = { 60 };
+-static const int en7581_pcie_reset1_pins[] = { 61 };
+-static const int en7581_pcie_reset2_pins[] = { 62 };
+-
+-static const struct pingroup en7581_pinctrl_groups[] = {
+-      PINCTRL_PIN_GROUP("pon", en7581_pon),
+-      PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps),
+-      PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps),
+-      PINCTRL_PIN_GROUP("sipo", en7581_sipo),
+-      PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk),
+-      PINCTRL_PIN_GROUP("mdio", en7581_mdio),
+-      PINCTRL_PIN_GROUP("uart2", en7581_uart2),
+-      PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts),
+-      PINCTRL_PIN_GROUP("hsuart", en7581_hsuart),
+-      PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts),
+-      PINCTRL_PIN_GROUP("uart4", en7581_uart4),
+-      PINCTRL_PIN_GROUP("uart5", en7581_uart5),
+-      PINCTRL_PIN_GROUP("i2c0", en7581_i2c0),
+-      PINCTRL_PIN_GROUP("i2c1", en7581_i2c1),
+-      PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi),
+-      PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd),
+-      PINCTRL_PIN_GROUP("i2s", en7581_i2s),
+-      PINCTRL_PIN_GROUP("pcm1", en7581_pcm1),
+-      PINCTRL_PIN_GROUP("pcm2", en7581_pcm2),
+-      PINCTRL_PIN_GROUP("spi", en7581_spi),
+-      PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad),
+-      PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi),
+-      PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int),
+-      PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4),
+-      PINCTRL_PIN_GROUP("emmc", en7581_emmc),
+-      PINCTRL_PIN_GROUP("pnand", en7581_pnand),
+-      PINCTRL_PIN_GROUP("gpio0", en7581_gpio0),
+-      PINCTRL_PIN_GROUP("gpio1", en7581_gpio1),
+-      PINCTRL_PIN_GROUP("gpio2", en7581_gpio2),
+-      PINCTRL_PIN_GROUP("gpio3", en7581_gpio3),
+-      PINCTRL_PIN_GROUP("gpio4", en7581_gpio4),
+-      PINCTRL_PIN_GROUP("gpio5", en7581_gpio5),
+-      PINCTRL_PIN_GROUP("gpio6", en7581_gpio6),
+-      PINCTRL_PIN_GROUP("gpio7", en7581_gpio7),
+-      PINCTRL_PIN_GROUP("gpio8", en7581_gpio8),
+-      PINCTRL_PIN_GROUP("gpio9", en7581_gpio9),
+-      PINCTRL_PIN_GROUP("gpio10", en7581_gpio10),
+-      PINCTRL_PIN_GROUP("gpio11", en7581_gpio11),
+-      PINCTRL_PIN_GROUP("gpio12", en7581_gpio12),
+-      PINCTRL_PIN_GROUP("gpio13", en7581_gpio13),
+-      PINCTRL_PIN_GROUP("gpio14", en7581_gpio14),
+-      PINCTRL_PIN_GROUP("gpio15", en7581_gpio15),
+-      PINCTRL_PIN_GROUP("gpio16", en7581_gpio16),
+-      PINCTRL_PIN_GROUP("gpio17", en7581_gpio17),
+-      PINCTRL_PIN_GROUP("gpio18", en7581_gpio18),
+-      PINCTRL_PIN_GROUP("gpio19", en7581_gpio19),
+-      PINCTRL_PIN_GROUP("gpio20", en7581_gpio20),
+-      PINCTRL_PIN_GROUP("gpio21", en7581_gpio21),
+-      PINCTRL_PIN_GROUP("gpio22", en7581_gpio22),
+-      PINCTRL_PIN_GROUP("gpio23", en7581_gpio23),
+-      PINCTRL_PIN_GROUP("gpio24", en7581_gpio24),
+-      PINCTRL_PIN_GROUP("gpio25", en7581_gpio25),
+-      PINCTRL_PIN_GROUP("gpio26", en7581_gpio26),
+-      PINCTRL_PIN_GROUP("gpio27", en7581_gpio27),
+-      PINCTRL_PIN_GROUP("gpio28", en7581_gpio28),
+-      PINCTRL_PIN_GROUP("gpio29", en7581_gpio29),
+-      PINCTRL_PIN_GROUP("gpio30", en7581_gpio30),
+-      PINCTRL_PIN_GROUP("gpio31", en7581_gpio31),
+-      PINCTRL_PIN_GROUP("gpio32", en7581_gpio32),
+-      PINCTRL_PIN_GROUP("gpio33", en7581_gpio33),
+-      PINCTRL_PIN_GROUP("gpio34", en7581_gpio34),
+-      PINCTRL_PIN_GROUP("gpio35", en7581_gpio35),
+-      PINCTRL_PIN_GROUP("gpio36", en7581_gpio36),
+-      PINCTRL_PIN_GROUP("gpio37", en7581_gpio37),
+-      PINCTRL_PIN_GROUP("gpio38", en7581_gpio38),
+-      PINCTRL_PIN_GROUP("gpio39", en7581_gpio39),
+-      PINCTRL_PIN_GROUP("gpio40", en7581_gpio40),
+-      PINCTRL_PIN_GROUP("gpio41", en7581_gpio41),
+-      PINCTRL_PIN_GROUP("gpio42", en7581_gpio42),
+-      PINCTRL_PIN_GROUP("gpio43", en7581_gpio43),
+-      PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
+-      PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
+-      PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
+-      PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
+-      PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
+-      PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
+-      PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
+-      PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
+-      PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
++static const int gpio0_pins[] = { 13 };
++static const int gpio1_pins[] = { 14 };
++static const int gpio2_pins[] = { 15 };
++static const int gpio3_pins[] = { 16 };
++static const int gpio4_pins[] = { 17 };
++static const int gpio5_pins[] = { 18 };
++static const int gpio6_pins[] = { 19 };
++static const int gpio7_pins[] = { 20 };
++static const int gpio8_pins[] = { 21 };
++static const int gpio9_pins[] = { 22 };
++static const int gpio10_pins[] = { 23 };
++static const int gpio11_pins[] = { 24 };
++static const int gpio12_pins[] = { 25 };
++static const int gpio13_pins[] = { 26 };
++static const int gpio14_pins[] = { 27 };
++static const int gpio15_pins[] = { 28 };
++static const int gpio16_pins[] = { 29 };
++static const int gpio17_pins[] = { 30 };
++static const int gpio18_pins[] = { 31 };
++static const int gpio19_pins[] = { 32 };
++static const int gpio20_pins[] = { 33 };
++static const int gpio21_pins[] = { 34 };
++static const int gpio22_pins[] = { 35 };
++static const int gpio23_pins[] = { 36 };
++static const int gpio24_pins[] = { 37 };
++static const int gpio25_pins[] = { 38 };
++static const int gpio26_pins[] = { 39 };
++static const int gpio27_pins[] = { 40 };
++static const int gpio28_pins[] = { 41 };
++static const int gpio29_pins[] = { 42 };
++static const int gpio30_pins[] = { 43 };
++static const int gpio31_pins[] = { 44 };
++static const int gpio32_pins[] = { 45 };
++static const int gpio33_pins[] = { 46 };
++static const int gpio34_pins[] = { 47 };
++static const int gpio35_pins[] = { 48 };
++static const int gpio36_pins[] = { 49 };
++static const int gpio37_pins[] = { 50 };
++static const int gpio38_pins[] = { 51 };
++static const int gpio39_pins[] = { 52 };
++static const int gpio40_pins[] = { 53 };
++static const int gpio41_pins[] = { 54 };
++static const int gpio42_pins[] = { 55 };
++static const int gpio43_pins[] = { 56 };
++static const int gpio44_pins[] = { 57 };
++static const int gpio45_pins[] = { 58 };
++static const int gpio46_pins[] = { 59 };
++static const int gpio47_pins[] = { 60 };
++static const int gpio48_pins[] = { 61 };
++static const int gpio49_pins[] = { 62 };
++static const int pcie_reset0_pins[] = { 60 };
++static const int pcie_reset1_pins[] = { 61 };
++static const int pcie_reset2_pins[] = { 62 };
++
++static const struct pingroup pinctrl_groups[] = {
++      PINCTRL_PIN_GROUP("pon", pon),
++      PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
++      PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
++      PINCTRL_PIN_GROUP("sipo", sipo),
++      PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
++      PINCTRL_PIN_GROUP("mdio", mdio),
++      PINCTRL_PIN_GROUP("uart2", uart2),
++      PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
++      PINCTRL_PIN_GROUP("hsuart", hsuart),
++      PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
++      PINCTRL_PIN_GROUP("uart4", uart4),
++      PINCTRL_PIN_GROUP("uart5", uart5),
++      PINCTRL_PIN_GROUP("i2c0", i2c0),
++      PINCTRL_PIN_GROUP("i2c1", i2c1),
++      PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
++      PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
++      PINCTRL_PIN_GROUP("i2s", i2s),
++      PINCTRL_PIN_GROUP("pcm1", pcm1),
++      PINCTRL_PIN_GROUP("pcm2", pcm2),
++      PINCTRL_PIN_GROUP("spi", spi),
++      PINCTRL_PIN_GROUP("spi_quad", spi_quad),
++      PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
++      PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
++      PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
++      PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2),
++      PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
++      PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
++      PINCTRL_PIN_GROUP("emmc", emmc),
++      PINCTRL_PIN_GROUP("pnand", pnand),
++      PINCTRL_PIN_GROUP("gpio0", gpio0),
++      PINCTRL_PIN_GROUP("gpio1", gpio1),
++      PINCTRL_PIN_GROUP("gpio2", gpio2),
++      PINCTRL_PIN_GROUP("gpio3", gpio3),
++      PINCTRL_PIN_GROUP("gpio4", gpio4),
++      PINCTRL_PIN_GROUP("gpio5", gpio5),
++      PINCTRL_PIN_GROUP("gpio6", gpio6),
++      PINCTRL_PIN_GROUP("gpio7", gpio7),
++      PINCTRL_PIN_GROUP("gpio8", gpio8),
++      PINCTRL_PIN_GROUP("gpio9", gpio9),
++      PINCTRL_PIN_GROUP("gpio10", gpio10),
++      PINCTRL_PIN_GROUP("gpio11", gpio11),
++      PINCTRL_PIN_GROUP("gpio12", gpio12),
++      PINCTRL_PIN_GROUP("gpio13", gpio13),
++      PINCTRL_PIN_GROUP("gpio14", gpio14),
++      PINCTRL_PIN_GROUP("gpio15", gpio15),
++      PINCTRL_PIN_GROUP("gpio16", gpio16),
++      PINCTRL_PIN_GROUP("gpio17", gpio17),
++      PINCTRL_PIN_GROUP("gpio18", gpio18),
++      PINCTRL_PIN_GROUP("gpio19", gpio19),
++      PINCTRL_PIN_GROUP("gpio20", gpio20),
++      PINCTRL_PIN_GROUP("gpio21", gpio21),
++      PINCTRL_PIN_GROUP("gpio22", gpio22),
++      PINCTRL_PIN_GROUP("gpio23", gpio23),
++      PINCTRL_PIN_GROUP("gpio24", gpio24),
++      PINCTRL_PIN_GROUP("gpio25", gpio25),
++      PINCTRL_PIN_GROUP("gpio26", gpio26),
++      PINCTRL_PIN_GROUP("gpio27", gpio27),
++      PINCTRL_PIN_GROUP("gpio28", gpio28),
++      PINCTRL_PIN_GROUP("gpio29", gpio29),
++      PINCTRL_PIN_GROUP("gpio30", gpio30),
++      PINCTRL_PIN_GROUP("gpio31", gpio31),
++      PINCTRL_PIN_GROUP("gpio32", gpio32),
++      PINCTRL_PIN_GROUP("gpio33", gpio33),
++      PINCTRL_PIN_GROUP("gpio34", gpio34),
++      PINCTRL_PIN_GROUP("gpio35", gpio35),
++      PINCTRL_PIN_GROUP("gpio36", gpio36),
++      PINCTRL_PIN_GROUP("gpio37", gpio37),
++      PINCTRL_PIN_GROUP("gpio38", gpio38),
++      PINCTRL_PIN_GROUP("gpio39", gpio39),
++      PINCTRL_PIN_GROUP("gpio40", gpio40),
++      PINCTRL_PIN_GROUP("gpio41", gpio41),
++      PINCTRL_PIN_GROUP("gpio42", gpio42),
++      PINCTRL_PIN_GROUP("gpio43", gpio43),
++      PINCTRL_PIN_GROUP("gpio44", gpio44),
++      PINCTRL_PIN_GROUP("gpio45", gpio45),
++      PINCTRL_PIN_GROUP("gpio46", gpio46),
++      PINCTRL_PIN_GROUP("gpio47", gpio47),
++      PINCTRL_PIN_GROUP("gpio48", gpio48),
++      PINCTRL_PIN_GROUP("gpio49", gpio49),
++      PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
++      PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
++      PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2),
+ };
+ 
+ static const char *const pon_groups[] = { "pon" };
+@@ -1154,7 +1154,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ };
+ 
+-static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
++static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+       PINCTRL_FUNC_DESC("pon", pon),
+       PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+       PINCTRL_FUNC_DESC("sipo", sipo),
+@@ -1181,7 +1181,7 @@ static const struct airoha_pinctrl_func
+       PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+ };
+ 
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+       PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+@@ -1242,7 +1242,7 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+       PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+@@ -1303,7 +1303,7 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+       PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+@@ -1364,7 +1364,7 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+       PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
+       PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+       PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+@@ -1425,47 +1425,47 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
+       PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+       PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+       PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = {
++static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+       .pinctrl_name = KBUILD_MODNAME,
+       .pinctrl_owner = THIS_MODULE,
+-      .pins = en7581_pinctrl_pins,
+-      .num_pins = ARRAY_SIZE(en7581_pinctrl_pins),
+-      .grps = en7581_pinctrl_groups,
+-      .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
+-      .funcs = en7581_pinctrl_funcs,
+-      .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
++      .pins = pinctrl_pins,
++      .num_pins = ARRAY_SIZE(pinctrl_pins),
++      .grps = pinctrl_groups,
++      .num_grps = ARRAY_SIZE(pinctrl_groups),
++      .funcs = pinctrl_funcs,
++      .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+       .confs_info = {
+               [AIROHA_PINCTRL_CONFS_PULLUP] = {
+-                      .confs = en7581_pinctrl_pullup_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf),
++                      .confs = pinctrl_pullup_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+-                      .confs = en7581_pinctrl_pulldown_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf),
++                      .confs = pinctrl_pulldown_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+-                      .confs = en7581_pinctrl_drive_e2_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf),
++                      .confs = pinctrl_drive_e2_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+-                      .confs = en7581_pinctrl_drive_e4_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf),
++                      .confs = pinctrl_drive_e4_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+-                      .confs = en7581_pinctrl_pcie_rst_od_conf,
+-                      .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf),
++                      .confs = pinctrl_pcie_rst_od_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
+               },
+       },
+ };
+ 
+ static const struct of_device_id airoha_pinctrl_of_match[] = {
+-      { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data },
++      { .compatible = "airoha,en7581-pinctrl", .data = &pinctrl_match_data },
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);

diff --git a/target/linux/airoha/patches-6.18/202-22-v7.3-pinctrl-airoha-an7583-remove-an7583-prefix-from-.patch b/target/linux/airoha/patches-6.18/202-22-v7.3-pinctrl-airoha-an7583-remove-an7583-prefix-from-.patch
new file mode 100644 (file)
index 0000000..ed814e1
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-22-v7.3-pinctrl-airoha-an7583-remove-an7583-prefix-from-.patch
@@ -0,0 +1,1010 @@
+From 978f66a006027481d51c849335609d637abf6f19 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Thu, 4 Jun 2026 07:58:46 +0300
+Subject: [PATCH v11 27/37] pinctrl: airoha: an7583: remove an7583 prefix from
+ variable names and definitions
+
+We have only an7583 specific code in the pinctrl-an7583 kernel module,
+so an7583 prefix is not necessary anymore. Remove it.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 616 ++++++++++++------------
+ 1 file changed, 308 insertions(+), 308 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -24,7 +24,7 @@
+ #define GPIO_MDC_IO_MASTER_MODE_MASK          BIT(22)
+ #define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
+ #define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
+-#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK     BIT(18)
++#define GPIO_PCM_SPI_CS2_MODE_MASK            BIT(18)
+ #define GPIO_PCM_SPI_CS1_MODE_MASK            BIT(17)
+ #define GPIO_PCM_SPI_MODE_MASK                        BIT(16)
+ #define GPIO_PCM2_MODE_MASK                   BIT(13)
+@@ -38,18 +38,18 @@
+ #define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
+ 
+ #define REG_GPIO_PON_MODE                     0x021c
+-#define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
+-#define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
+-#define AN7583_UART_RXD_GPIO_MODE_MASK                BIT(24)
+-#define AN7583_UART_TXD_GPIO_MODE_MASK                BIT(23)
+-#define AN7583_SPI_MISO_GPIO_MODE_MASK                BIT(22)
+-#define AN7583_SPI_MOSI_GPIO_MODE_MASK                BIT(21)
+-#define AN7583_SPI_CS_GPIO_MODE_MASK          BIT(20)
+-#define AN7583_SPI_CLK_GPIO_MODE_MASK         BIT(19)
+-#define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
+-#define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
+-#define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
+-#define AN7583_I2C0_SCL_GPIO_MODE_MASK                BIT(15)
++#define MDIO_0_GPIO_MODE_MASK                 BIT(26)
++#define MDC_0_GPIO_MODE_MASK                  BIT(25)
++#define UART_RXD_GPIO_MODE_MASK                       BIT(24)
++#define UART_TXD_GPIO_MODE_MASK                       BIT(23)
++#define SPI_MISO_GPIO_MODE_MASK                       BIT(22)
++#define SPI_MOSI_GPIO_MODE_MASK                       BIT(21)
++#define SPI_CS_GPIO_MODE_MASK                 BIT(20)
++#define SPI_CLK_GPIO_MODE_MASK                        BIT(19)
++#define I2C1_SDA_GPIO_MODE_MASK                       BIT(18)
++#define I2C1_SCL_GPIO_MODE_MASK                       BIT(17)
++#define I2C0_SDA_GPIO_MODE_MASK                       BIT(16)
++#define I2C0_SCL_GPIO_MODE_MASK                       BIT(15)
+ #define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
+ #define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
+ #define SIPO_RCLK_MODE_MASK                   BIT(11)
+@@ -93,32 +93,32 @@
+ 
+ /* CONF */
+ #define REG_I2C_SDA_E2                                0x001c
+-#define AN7583_I2C1_SCL_E2_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_E2_MASK                       BIT(15)
++#define I2C1_SCL_E2_MASK                      BIT(16)
++#define I2C1_SDA_E2_MASK                      BIT(15)
+ #define SPI_MISO_E2_MASK                      BIT(14)
+ #define SPI_MOSI_E2_MASK                      BIT(13)
+ #define SPI_CLK_E2_MASK                               BIT(12)
+ #define SPI_CS0_E2_MASK                               BIT(11)
+ #define PCIE1_RESET_E2_MASK                   BIT(9)
+ #define PCIE0_RESET_E2_MASK                   BIT(8)
+-#define AN7583_MDIO_0_E2_MASK                 BIT(5)
+-#define AN7583_MDC_0_E2_MASK                  BIT(4)
++#define MDIO_0_E2_MASK                                BIT(5)
++#define MDC_0_E2_MASK                         BIT(4)
+ #define UART1_RXD_E2_MASK                     BIT(3)
+ #define UART1_TXD_E2_MASK                     BIT(2)
+ #define I2C_SCL_E2_MASK                               BIT(1)
+ #define I2C_SDA_E2_MASK                               BIT(0)
+ 
+ #define REG_I2C_SDA_E4                                0x0020
+-#define AN7583_I2C1_SCL_E4_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_E4_MASK                       BIT(15)
++#define I2C1_SCL_E4_MASK                      BIT(16)
++#define I2C1_SDA_E4_MASK                      BIT(15)
+ #define SPI_MISO_E4_MASK                      BIT(14)
+ #define SPI_MOSI_E4_MASK                      BIT(13)
+ #define SPI_CLK_E4_MASK                               BIT(12)
+ #define SPI_CS0_E4_MASK                               BIT(11)
+ #define PCIE1_RESET_E4_MASK                   BIT(9)
+ #define PCIE0_RESET_E4_MASK                   BIT(8)
+-#define AN7583_MDIO_0_E4_MASK                 BIT(5)
+-#define AN7583_MDC_0_E4_MASK                  BIT(4)
++#define MDIO_0_E4_MASK                                BIT(5)
++#define MDC_0_E4_MASK                         BIT(4)
+ #define UART1_RXD_E4_MASK                     BIT(3)
+ #define UART1_TXD_E4_MASK                     BIT(2)
+ #define I2C_SCL_E4_MASK                               BIT(1)
+@@ -130,32 +130,32 @@
+ #define REG_GPIO_H_E4                         0x0030
+ 
+ #define REG_I2C_SDA_PU                                0x0044
+-#define AN7583_I2C1_SCL_PU_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_PU_MASK                       BIT(15)
++#define I2C1_SCL_PU_MASK                      BIT(16)
++#define I2C1_SDA_PU_MASK                      BIT(15)
+ #define SPI_MISO_PU_MASK                      BIT(14)
+ #define SPI_MOSI_PU_MASK                      BIT(13)
+ #define SPI_CLK_PU_MASK                               BIT(12)
+ #define SPI_CS0_PU_MASK                               BIT(11)
+ #define PCIE1_RESET_PU_MASK                   BIT(9)
+ #define PCIE0_RESET_PU_MASK                   BIT(8)
+-#define AN7583_MDIO_0_PU_MASK                 BIT(5)
+-#define AN7583_MDC_0_PU_MASK                  BIT(4)
++#define MDIO_0_PU_MASK                                BIT(5)
++#define MDC_0_PU_MASK                         BIT(4)
+ #define UART1_RXD_PU_MASK                     BIT(3)
+ #define UART1_TXD_PU_MASK                     BIT(2)
+ #define I2C_SCL_PU_MASK                               BIT(1)
+ #define I2C_SDA_PU_MASK                               BIT(0)
+ 
+ #define REG_I2C_SDA_PD                                0x0048
+-#define AN7583_I2C1_SCL_PD_MASK                       BIT(16)
+-#define AN7583_I2C1_SDA_PD_MASK                       BIT(15)
++#define I2C1_SCL_PD_MASK                      BIT(16)
++#define I2C1_SDA_PD_MASK                      BIT(15)
+ #define SPI_MISO_PD_MASK                      BIT(14)
+ #define SPI_MOSI_PD_MASK                      BIT(13)
+ #define SPI_CLK_PD_MASK                               BIT(12)
+ #define SPI_CS0_PD_MASK                               BIT(11)
+ #define PCIE1_RESET_PD_MASK                   BIT(9)
+ #define PCIE0_RESET_PD_MASK                   BIT(8)
+-#define AN7583_MDIO_0_PD_MASK                 BIT(5)
+-#define AN7583_MDC_0_PD_MASK                  BIT(4)
++#define MDIO_0_PD_MASK                                BIT(5)
++#define MDC_0_PD_MASK                         BIT(4)
+ #define UART1_RXD_PD_MASK                     BIT(3)
+ #define UART1_TXD_PD_MASK                     BIT(2)
+ #define I2C_SCL_PD_MASK                               BIT(1)
+@@ -333,7 +333,7 @@
+               .regmap_size = 2,                                       \
+       }
+ 
+-static struct pinctrl_pin_desc an7583_pinctrl_pins[] = {
++static struct pinctrl_pin_desc pinctrl_pins[] = {
+       PINCTRL_PIN(2, "gpio0"),
+       PINCTRL_PIN(3, "gpio1"),
+       PINCTRL_PIN(4, "gpio2"),
+@@ -389,178 +389,178 @@ static struct pinctrl_pin_desc an7583_pi
+       PINCTRL_PIN(54, "mdio_0"),
+ };
+ 
+-static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+-static const int an7583_pon_tod_1pps_pins[] = { 32 };
+-static const int an7583_gsw_tod_1pps_pins[] = { 32 };
+-static const int an7583_sipo_pins[] = { 34, 35 };
+-static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 };
+-static const int an7583_mdio_pins[] = { 53, 54 };
+-static const int an7583_mdio1_pins[] = { 43, 44 };
+-static const int an7583_uart2_pins[] = { 34, 35 };
+-static const int an7583_uart2_cts_rts_pins[] = { 32, 33 };
+-static const int an7583_hsuart_pins[] = { 30, 31 };
+-static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 };
+-static const int an7583_npu_uart_pins[] = { 7, 8 };
+-static const int an7583_uart4_pins[] = { 7, 8 };
+-static const int an7583_uart5_pins[] = { 23, 24 };
+-static const int an7583_i2c0_pins[] = { 41, 42 };
+-static const int an7583_i2c1_pins[] = { 43, 44 };
+-static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
+-static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
+-static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
+-static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
+-static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
+-static const int an7583_spi_quad_pins[] = { 25, 26 };
+-static const int an7583_spi_cs1_pins[] = { 27 };
+-static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
+-static const int an7583_pcm_spi_rst_pins[] = { 14 };
+-static const int an7583_pcm_spi_cs1_pins[] = { 24 };
+-static const int an7583_emmc_pins[] = {
++static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
++static const int pon_tod_1pps_pins[] = { 32 };
++static const int gsw_tod_1pps_pins[] = { 32 };
++static const int sipo_pins[] = { 34, 35 };
++static const int sipo_rclk_pins[] = { 34, 35, 33 };
++static const int mdio_pins[] = { 53, 54 };
++static const int mdio1_pins[] = { 43, 44 };
++static const int uart2_pins[] = { 34, 35 };
++static const int uart2_cts_rts_pins[] = { 32, 33 };
++static const int hsuart_pins[] = { 30, 31 };
++static const int hsuart_cts_rts_pins[] = { 28, 29 };
++static const int npu_uart_pins[] = { 7, 8 };
++static const int uart4_pins[] = { 7, 8 };
++static const int uart5_pins[] = { 23, 24 };
++static const int i2c0_pins[] = { 41, 42 };
++static const int i2c1_pins[] = { 43, 44 };
++static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 };
++static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
++static const int pcm1_pins[] = { 10, 11, 12, 13, 14 };
++static const int pcm2_pins[] = { 28, 29, 30, 31, 24 };
++static const int spi_pins[] = { 45, 46, 47, 48 };
++static const int spi_quad_pins[] = { 25, 26 };
++static const int spi_cs1_pins[] = { 27 };
++static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
++static const int pcm_spi_rst_pins[] = { 14 };
++static const int pcm_spi_cs1_pins[] = { 24 };
++static const int emmc_pins[] = {
+       7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47
+ };
+-static const int an7583_pnand_pins[] = {
++static const int pnand_pins[] = {
+       7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48
+ };
+-static const int an7583_gpio0_pins[] = { 2 };
+-static const int an7583_gpio1_pins[] = { 3 };
+-static const int an7583_gpio2_pins[] = { 4 };
+-static const int an7583_gpio3_pins[] = { 5 };
+-static const int an7583_gpio4_pins[] = { 6 };
+-static const int an7583_gpio5_pins[] = { 7 };
+-static const int an7583_gpio6_pins[] = { 8 };
+-static const int an7583_gpio7_pins[] = { 9 };
+-static const int an7583_gpio8_pins[] = { 10 };
+-static const int an7583_gpio9_pins[] = { 11 };
+-static const int an7583_gpio10_pins[] = { 12 };
+-static const int an7583_gpio11_pins[] = { 13 };
+-static const int an7583_gpio12_pins[] = { 14 };
+-static const int an7583_gpio13_pins[] = { 15 };
+-static const int an7583_gpio14_pins[] = { 16 };
+-static const int an7583_gpio15_pins[] = { 17 };
+-static const int an7583_gpio16_pins[] = { 18 };
+-static const int an7583_gpio17_pins[] = { 19 };
+-static const int an7583_gpio18_pins[] = { 20 };
+-static const int an7583_gpio19_pins[] = { 21 };
+-static const int an7583_gpio20_pins[] = { 22 };
+-static const int an7583_gpio21_pins[] = { 23 };
+-static const int an7583_gpio22_pins[] = { 24 };
+-static const int an7583_gpio23_pins[] = { 25 };
+-static const int an7583_gpio24_pins[] = { 26 };
+-static const int an7583_gpio25_pins[] = { 27 };
+-static const int an7583_gpio26_pins[] = { 28 };
+-static const int an7583_gpio27_pins[] = { 29 };
+-static const int an7583_gpio28_pins[] = { 30 };
+-static const int an7583_gpio29_pins[] = { 31 };
+-static const int an7583_gpio30_pins[] = { 32 };
+-static const int an7583_gpio31_pins[] = { 33 };
+-static const int an7583_gpio32_pins[] = { 34 };
+-static const int an7583_gpio33_pins[] = { 35 };
+-static const int an7583_gpio34_pins[] = { 36 };
+-static const int an7583_gpio35_pins[] = { 37 };
+-static const int an7583_gpio36_pins[] = { 38 };
+-static const int an7583_gpio37_pins[] = { 39 };
+-static const int an7583_gpio38_pins[] = { 40 };
+-static const int an7583_gpio39_pins[] = { 41 };
+-static const int an7583_gpio40_pins[] = { 42 };
+-static const int an7583_gpio41_pins[] = { 43 };
+-static const int an7583_gpio42_pins[] = { 44 };
+-static const int an7583_gpio43_pins[] = { 45 };
+-static const int an7583_gpio44_pins[] = { 46 };
+-static const int an7583_gpio45_pins[] = { 47 };
+-static const int an7583_gpio46_pins[] = { 48 };
+-static const int an7583_gpio47_pins[] = { 49 };
+-static const int an7583_gpio48_pins[] = { 50 };
+-static const int an7583_gpio49_pins[] = { 51 };
+-static const int an7583_gpio50_pins[] = { 52 };
+-static const int an7583_gpio51_pins[] = { 53 };
+-static const int an7583_gpio52_pins[] = { 54 };
+-static const int an7583_pcie_reset0_pins[] = { 51 };
+-static const int an7583_pcie_reset1_pins[] = { 52 };
+-
+-static const struct pingroup an7583_pinctrl_groups[] = {
+-      PINCTRL_PIN_GROUP("pon", an7583_pon),
+-      PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps),
+-      PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps),
+-      PINCTRL_PIN_GROUP("sipo", an7583_sipo),
+-      PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk),
+-      PINCTRL_PIN_GROUP("mdio", an7583_mdio),
+-      PINCTRL_PIN_GROUP("mdio1", an7583_mdio1),
+-      PINCTRL_PIN_GROUP("uart2", an7583_uart2),
+-      PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts),
+-      PINCTRL_PIN_GROUP("hsuart", an7583_hsuart),
+-      PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts),
+-      PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart),
+-      PINCTRL_PIN_GROUP("uart4", an7583_uart4),
+-      PINCTRL_PIN_GROUP("uart5", an7583_uart5),
+-      PINCTRL_PIN_GROUP("i2c0", an7583_i2c0),
+-      PINCTRL_PIN_GROUP("i2c1", an7583_i2c1),
+-      PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi),
+-      PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd),
+-      PINCTRL_PIN_GROUP("pcm1", an7583_pcm1),
+-      PINCTRL_PIN_GROUP("pcm2", an7583_pcm2),
+-      PINCTRL_PIN_GROUP("spi", an7583_spi),
+-      PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad),
+-      PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1),
+-      PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi),
+-      PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst),
+-      PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1),
+-      PINCTRL_PIN_GROUP("emmc", an7583_emmc),
+-      PINCTRL_PIN_GROUP("pnand", an7583_pnand),
+-      PINCTRL_PIN_GROUP("gpio0", an7583_gpio0),
+-      PINCTRL_PIN_GROUP("gpio1", an7583_gpio1),
+-      PINCTRL_PIN_GROUP("gpio2", an7583_gpio2),
+-      PINCTRL_PIN_GROUP("gpio3", an7583_gpio3),
+-      PINCTRL_PIN_GROUP("gpio4", an7583_gpio4),
+-      PINCTRL_PIN_GROUP("gpio5", an7583_gpio5),
+-      PINCTRL_PIN_GROUP("gpio6", an7583_gpio6),
+-      PINCTRL_PIN_GROUP("gpio7", an7583_gpio7),
+-      PINCTRL_PIN_GROUP("gpio8", an7583_gpio8),
+-      PINCTRL_PIN_GROUP("gpio9", an7583_gpio9),
+-      PINCTRL_PIN_GROUP("gpio10", an7583_gpio10),
+-      PINCTRL_PIN_GROUP("gpio11", an7583_gpio11),
+-      PINCTRL_PIN_GROUP("gpio12", an7583_gpio12),
+-      PINCTRL_PIN_GROUP("gpio13", an7583_gpio13),
+-      PINCTRL_PIN_GROUP("gpio14", an7583_gpio14),
+-      PINCTRL_PIN_GROUP("gpio15", an7583_gpio15),
+-      PINCTRL_PIN_GROUP("gpio16", an7583_gpio16),
+-      PINCTRL_PIN_GROUP("gpio17", an7583_gpio17),
+-      PINCTRL_PIN_GROUP("gpio18", an7583_gpio18),
+-      PINCTRL_PIN_GROUP("gpio19", an7583_gpio19),
+-      PINCTRL_PIN_GROUP("gpio20", an7583_gpio20),
+-      PINCTRL_PIN_GROUP("gpio21", an7583_gpio21),
+-      PINCTRL_PIN_GROUP("gpio22", an7583_gpio22),
+-      PINCTRL_PIN_GROUP("gpio23", an7583_gpio23),
+-      PINCTRL_PIN_GROUP("gpio24", an7583_gpio24),
+-      PINCTRL_PIN_GROUP("gpio25", an7583_gpio25),
+-      PINCTRL_PIN_GROUP("gpio26", an7583_gpio26),
+-      PINCTRL_PIN_GROUP("gpio27", an7583_gpio27),
+-      PINCTRL_PIN_GROUP("gpio28", an7583_gpio28),
+-      PINCTRL_PIN_GROUP("gpio29", an7583_gpio29),
+-      PINCTRL_PIN_GROUP("gpio30", an7583_gpio30),
+-      PINCTRL_PIN_GROUP("gpio31", an7583_gpio31),
+-      PINCTRL_PIN_GROUP("gpio32", an7583_gpio32),
+-      PINCTRL_PIN_GROUP("gpio33", an7583_gpio33),
+-      PINCTRL_PIN_GROUP("gpio34", an7583_gpio34),
+-      PINCTRL_PIN_GROUP("gpio35", an7583_gpio35),
+-      PINCTRL_PIN_GROUP("gpio36", an7583_gpio36),
+-      PINCTRL_PIN_GROUP("gpio37", an7583_gpio37),
+-      PINCTRL_PIN_GROUP("gpio38", an7583_gpio38),
+-      PINCTRL_PIN_GROUP("gpio39", an7583_gpio39),
+-      PINCTRL_PIN_GROUP("gpio40", an7583_gpio40),
+-      PINCTRL_PIN_GROUP("gpio41", an7583_gpio41),
+-      PINCTRL_PIN_GROUP("gpio42", an7583_gpio42),
+-      PINCTRL_PIN_GROUP("gpio43", an7583_gpio43),
+-      PINCTRL_PIN_GROUP("gpio44", an7583_gpio44),
+-      PINCTRL_PIN_GROUP("gpio45", an7583_gpio45),
+-      PINCTRL_PIN_GROUP("gpio46", an7583_gpio46),
+-      PINCTRL_PIN_GROUP("gpio47", an7583_gpio47),
+-      PINCTRL_PIN_GROUP("gpio48", an7583_gpio48),
+-      PINCTRL_PIN_GROUP("gpio49", an7583_gpio49),
+-      PINCTRL_PIN_GROUP("gpio50", an7583_gpio50),
+-      PINCTRL_PIN_GROUP("gpio51", an7583_gpio51),
+-      PINCTRL_PIN_GROUP("gpio52", an7583_gpio52),
+-      PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0),
+-      PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1),
++static const int gpio0_pins[] = { 2 };
++static const int gpio1_pins[] = { 3 };
++static const int gpio2_pins[] = { 4 };
++static const int gpio3_pins[] = { 5 };
++static const int gpio4_pins[] = { 6 };
++static const int gpio5_pins[] = { 7 };
++static const int gpio6_pins[] = { 8 };
++static const int gpio7_pins[] = { 9 };
++static const int gpio8_pins[] = { 10 };
++static const int gpio9_pins[] = { 11 };
++static const int gpio10_pins[] = { 12 };
++static const int gpio11_pins[] = { 13 };
++static const int gpio12_pins[] = { 14 };
++static const int gpio13_pins[] = { 15 };
++static const int gpio14_pins[] = { 16 };
++static const int gpio15_pins[] = { 17 };
++static const int gpio16_pins[] = { 18 };
++static const int gpio17_pins[] = { 19 };
++static const int gpio18_pins[] = { 20 };
++static const int gpio19_pins[] = { 21 };
++static const int gpio20_pins[] = { 22 };
++static const int gpio21_pins[] = { 23 };
++static const int gpio22_pins[] = { 24 };
++static const int gpio23_pins[] = { 25 };
++static const int gpio24_pins[] = { 26 };
++static const int gpio25_pins[] = { 27 };
++static const int gpio26_pins[] = { 28 };
++static const int gpio27_pins[] = { 29 };
++static const int gpio28_pins[] = { 30 };
++static const int gpio29_pins[] = { 31 };
++static const int gpio30_pins[] = { 32 };
++static const int gpio31_pins[] = { 33 };
++static const int gpio32_pins[] = { 34 };
++static const int gpio33_pins[] = { 35 };
++static const int gpio34_pins[] = { 36 };
++static const int gpio35_pins[] = { 37 };
++static const int gpio36_pins[] = { 38 };
++static const int gpio37_pins[] = { 39 };
++static const int gpio38_pins[] = { 40 };
++static const int gpio39_pins[] = { 41 };
++static const int gpio40_pins[] = { 42 };
++static const int gpio41_pins[] = { 43 };
++static const int gpio42_pins[] = { 44 };
++static const int gpio43_pins[] = { 45 };
++static const int gpio44_pins[] = { 46 };
++static const int gpio45_pins[] = { 47 };
++static const int gpio46_pins[] = { 48 };
++static const int gpio47_pins[] = { 49 };
++static const int gpio48_pins[] = { 50 };
++static const int gpio49_pins[] = { 51 };
++static const int gpio50_pins[] = { 52 };
++static const int gpio51_pins[] = { 53 };
++static const int gpio52_pins[] = { 54 };
++static const int pcie_reset0_pins[] = { 51 };
++static const int pcie_reset1_pins[] = { 52 };
++
++static const struct pingroup pinctrl_groups[] = {
++      PINCTRL_PIN_GROUP("pon", pon),
++      PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
++      PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
++      PINCTRL_PIN_GROUP("sipo", sipo),
++      PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
++      PINCTRL_PIN_GROUP("mdio", mdio),
++      PINCTRL_PIN_GROUP("mdio1", mdio1),
++      PINCTRL_PIN_GROUP("uart2", uart2),
++      PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts),
++      PINCTRL_PIN_GROUP("hsuart", hsuart),
++      PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts),
++      PINCTRL_PIN_GROUP("npu_uart", npu_uart),
++      PINCTRL_PIN_GROUP("uart4", uart4),
++      PINCTRL_PIN_GROUP("uart5", uart5),
++      PINCTRL_PIN_GROUP("i2c0", i2c0),
++      PINCTRL_PIN_GROUP("i2c1", i2c1),
++      PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
++      PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
++      PINCTRL_PIN_GROUP("pcm1", pcm1),
++      PINCTRL_PIN_GROUP("pcm2", pcm2),
++      PINCTRL_PIN_GROUP("spi", spi),
++      PINCTRL_PIN_GROUP("spi_quad", spi_quad),
++      PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
++      PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
++      PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
++      PINCTRL_PIN_GROUP("emmc", emmc),
++      PINCTRL_PIN_GROUP("pnand", pnand),
++      PINCTRL_PIN_GROUP("gpio0", gpio0),
++      PINCTRL_PIN_GROUP("gpio1", gpio1),
++      PINCTRL_PIN_GROUP("gpio2", gpio2),
++      PINCTRL_PIN_GROUP("gpio3", gpio3),
++      PINCTRL_PIN_GROUP("gpio4", gpio4),
++      PINCTRL_PIN_GROUP("gpio5", gpio5),
++      PINCTRL_PIN_GROUP("gpio6", gpio6),
++      PINCTRL_PIN_GROUP("gpio7", gpio7),
++      PINCTRL_PIN_GROUP("gpio8", gpio8),
++      PINCTRL_PIN_GROUP("gpio9", gpio9),
++      PINCTRL_PIN_GROUP("gpio10", gpio10),
++      PINCTRL_PIN_GROUP("gpio11", gpio11),
++      PINCTRL_PIN_GROUP("gpio12", gpio12),
++      PINCTRL_PIN_GROUP("gpio13", gpio13),
++      PINCTRL_PIN_GROUP("gpio14", gpio14),
++      PINCTRL_PIN_GROUP("gpio15", gpio15),
++      PINCTRL_PIN_GROUP("gpio16", gpio16),
++      PINCTRL_PIN_GROUP("gpio17", gpio17),
++      PINCTRL_PIN_GROUP("gpio18", gpio18),
++      PINCTRL_PIN_GROUP("gpio19", gpio19),
++      PINCTRL_PIN_GROUP("gpio20", gpio20),
++      PINCTRL_PIN_GROUP("gpio21", gpio21),
++      PINCTRL_PIN_GROUP("gpio22", gpio22),
++      PINCTRL_PIN_GROUP("gpio23", gpio23),
++      PINCTRL_PIN_GROUP("gpio24", gpio24),
++      PINCTRL_PIN_GROUP("gpio25", gpio25),
++      PINCTRL_PIN_GROUP("gpio26", gpio26),
++      PINCTRL_PIN_GROUP("gpio27", gpio27),
++      PINCTRL_PIN_GROUP("gpio28", gpio28),
++      PINCTRL_PIN_GROUP("gpio29", gpio29),
++      PINCTRL_PIN_GROUP("gpio30", gpio30),
++      PINCTRL_PIN_GROUP("gpio31", gpio31),
++      PINCTRL_PIN_GROUP("gpio32", gpio32),
++      PINCTRL_PIN_GROUP("gpio33", gpio33),
++      PINCTRL_PIN_GROUP("gpio34", gpio34),
++      PINCTRL_PIN_GROUP("gpio35", gpio35),
++      PINCTRL_PIN_GROUP("gpio36", gpio36),
++      PINCTRL_PIN_GROUP("gpio37", gpio37),
++      PINCTRL_PIN_GROUP("gpio38", gpio38),
++      PINCTRL_PIN_GROUP("gpio39", gpio39),
++      PINCTRL_PIN_GROUP("gpio40", gpio40),
++      PINCTRL_PIN_GROUP("gpio41", gpio41),
++      PINCTRL_PIN_GROUP("gpio42", gpio42),
++      PINCTRL_PIN_GROUP("gpio43", gpio43),
++      PINCTRL_PIN_GROUP("gpio44", gpio44),
++      PINCTRL_PIN_GROUP("gpio45", gpio45),
++      PINCTRL_PIN_GROUP("gpio46", gpio46),
++      PINCTRL_PIN_GROUP("gpio47", gpio47),
++      PINCTRL_PIN_GROUP("gpio48", gpio48),
++      PINCTRL_PIN_GROUP("gpio49", gpio49),
++      PINCTRL_PIN_GROUP("gpio50", gpio50),
++      PINCTRL_PIN_GROUP("gpio51", gpio51),
++      PINCTRL_PIN_GROUP("gpio52", gpio52),
++      PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
++      PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+ };
+ 
+ static const char *const pon_groups[] = { "pon" };
+@@ -568,29 +568,29 @@ static const char *const tod_1pps_groups
+       "pon_tod_1pps", "gsw_tod_1pps"
+ };
+ static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
+-static const char *const an7583_mdio_groups[] = { "mdio" };
++static const char *const mdio_groups[] = { "mdio" };
+ static const char *const uart_groups[] = {
+       "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+       "uart4", "uart5"
+ };
+-static const char *const an7583_i2c_groups[] = { "i2c0", "i2c1" };
++static const char *const i2c_groups[] = { "i2c0", "i2c1" };
+ static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+ static const char *const pcm_groups[] = { "pcm1", "pcm2" };
+ static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
+-static const char *const an7583_pcm_spi_groups[] = {
++static const char *const pcm_spi_groups[] = {
+       "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
+ };
+ static const char *const emmc_groups[] = { "emmc" };
+ static const char *const pnand_groups[] = { "pnand" };
+-static const char *const an7583_gpio_groups[] = {
++static const char *const gpio_groups[] = {
+       "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+       "gpio44", "gpio45", "gpio46", "gpio47", "gpio48",
+       "gpio49", "gpio50", "gpio51", "gpio52"
+ };
+-static const char *const an7583_pcie_reset_groups[] = {
++static const char *const pcie_reset_groups[] = {
+       "pcie_reset0", "pcie_reset1"
+ };
+-static const char *const an7583_pwm_groups[] = {
++static const char *const pwm_groups[] = {
+       "gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
+       "gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
+       "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
+@@ -600,28 +600,28 @@ static const char *const an7583_pwm_grou
+       "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
+       "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51"
+ };
+-static const char *const an7583_phy1_led0_groups[] = {
++static const char *const phy1_led0_groups[] = {
+       "gpio1", "gpio2", "gpio3", "gpio4"
+ };
+-static const char *const an7583_phy2_led0_groups[] = {
++static const char *const phy2_led0_groups[] = {
+       "gpio1", "gpio2", "gpio3", "gpio4"
+ };
+-static const char *const an7583_phy3_led0_groups[] = {
++static const char *const phy3_led0_groups[] = {
+       "gpio1", "gpio2", "gpio3", "gpio4"
+ };
+-static const char *const an7583_phy4_led0_groups[] = {
++static const char *const phy4_led0_groups[] = {
+       "gpio1", "gpio2", "gpio3", "gpio4"
+ };
+-static const char *const an7583_phy1_led1_groups[] = {
++static const char *const phy1_led1_groups[] = {
+       "gpio8", "gpio9", "gpio10", "gpio11"
+ };
+-static const char *const an7583_phy2_led1_groups[] = {
++static const char *const phy2_led1_groups[] = {
+       "gpio8", "gpio9", "gpio10", "gpio11"
+ };
+-static const char *const an7583_phy3_led1_groups[] = {
++static const char *const phy3_led1_groups[] = {
+       "gpio8", "gpio9", "gpio10", "gpio11"
+ };
+-static const char *const an7583_phy4_led1_groups[] = {
++static const char *const phy4_led1_groups[] = {
+       "gpio8", "gpio9", "gpio10", "gpio11"
+ };
+ 
+@@ -682,13 +682,13 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = {
++static const struct airoha_pinctrl_func_group mdio_func_group[] = {
+       {
+               .name = "mdio",
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+-                      AN7583_MDC_0_GPIO_MODE_MASK | AN7583_MDIO_0_GPIO_MODE_MASK,
++                      MDC_0_GPIO_MODE_MASK | MDIO_0_GPIO_MODE_MASK,
+                       0
+               },
+               .regmap_size = 1,
+@@ -754,13 +754,13 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_i2c_func_group[] = {
++static const struct airoha_pinctrl_func_group i2c_func_group[] = {
+       {
+               .name = "i2c0",
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+-                      AN7583_I2C0_SCL_GPIO_MODE_MASK | AN7583_I2C0_SDA_GPIO_MODE_MASK,
++                      I2C0_SCL_GPIO_MODE_MASK | I2C0_SDA_GPIO_MODE_MASK,
+                       0
+               },
+               .regmap_size = 1,
+@@ -769,7 +769,7 @@ static const struct airoha_pinctrl_func_
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+-                      AN7583_I2C1_SCL_GPIO_MODE_MASK | AN7583_I2C1_SDA_GPIO_MODE_MASK,
++                      I2C1_SCL_GPIO_MODE_MASK | I2C1_SDA_GPIO_MODE_MASK,
+                       0
+               },
+               .regmap_size = 1,
+@@ -869,7 +869,7 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = {
++static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
+       {
+               .name = "pcm_spi",
+               .regmap[0] = {
+@@ -911,8 +911,8 @@ static const struct airoha_pinctrl_func_
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_SPI_CS1_MODE,
+-                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
+-                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
++                      GPIO_PCM_SPI_CS2_MODE_MASK,
++                      GPIO_PCM_SPI_CS2_MODE_MASK
+               },
+               .regmap_size = 1,
+       }, {
+@@ -962,37 +962,37 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_gpio_func_group[] = {
++static const struct airoha_pinctrl_func_group gpio_func_group[] = {
+       AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG,
+-                              AN7583_I2C0_SCL_GPIO_MODE_MASK),
++                              I2C0_SCL_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG,
+-                              AN7583_I2C0_SDA_GPIO_MODE_MASK),
++                              I2C0_SDA_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG,
+-                              AN7583_I2C1_SCL_GPIO_MODE_MASK),
++                              I2C1_SCL_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG,
+-                              AN7583_I2C1_SDA_GPIO_MODE_MASK),
++                              I2C1_SDA_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG,
+-                              AN7583_SPI_CLK_GPIO_MODE_MASK),
++                              SPI_CLK_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG,
+-                              AN7583_SPI_CS_GPIO_MODE_MASK),
++                              SPI_CS_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG,
+-                              AN7583_SPI_MOSI_GPIO_MODE_MASK),
++                              SPI_MOSI_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG,
+-                              AN7583_SPI_MISO_GPIO_MODE_MASK),
++                              SPI_MISO_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
+-                              AN7583_UART_TXD_GPIO_MODE_MASK),
++                              UART_TXD_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
+-                              AN7583_UART_RXD_GPIO_MODE_MASK),
++                              UART_RXD_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
+                               GPIO_PCIE_RESET0_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG,
+                               GPIO_PCIE_RESET1_MASK),
+       AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG,
+-                              AN7583_MDC_0_GPIO_MODE_MASK),
+-      AIROHA_PINCTRL_GPIO("gpio52", AN7583_MDIO_0_GPIO_MODE_MASK),
++                              MDC_0_GPIO_MODE_MASK),
++      AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
++static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
+       {
+               .name = "pcie_reset0",
+               .regmap[0] = {
+@@ -1014,7 +1014,7 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
++static const struct airoha_pinctrl_func_group pwm_func_group[] = {
+       AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
+@@ -1051,34 +1051,34 @@ static const struct airoha_pinctrl_func_
+       AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG,
+-                                 AN7583_I2C0_SCL_GPIO_MODE_MASK),
++                                 I2C0_SCL_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG,
+-                                 AN7583_I2C0_SDA_GPIO_MODE_MASK),
++                                 I2C0_SDA_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG,
+-                                 AN7583_I2C1_SCL_GPIO_MODE_MASK),
++                                 I2C1_SCL_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG,
+-                                 AN7583_I2C1_SDA_GPIO_MODE_MASK),
++                                 I2C1_SDA_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG,
+-                                 AN7583_SPI_CLK_GPIO_MODE_MASK),
++                                 SPI_CLK_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG,
+-                                 AN7583_SPI_CS_GPIO_MODE_MASK),
++                                 SPI_CS_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG,
+-                                 AN7583_SPI_MOSI_GPIO_MODE_MASK),
++                                 SPI_MOSI_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG,
+-                                 AN7583_SPI_MISO_GPIO_MODE_MASK),
++                                 SPI_MISO_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
+-                                 AN7583_UART_TXD_GPIO_MODE_MASK),
++                                 UART_TXD_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
+-                                 AN7583_UART_RXD_GPIO_MODE_MASK),
++                                 UART_RXD_GPIO_MODE_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
+                                  GPIO_PCIE_RESET0_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG,
+                                  GPIO_PCIE_RESET1_MASK),
+       AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG,
+-                                 AN7583_MDC_0_GPIO_MODE_MASK),
++                                 MDC_0_GPIO_MODE_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = {
++static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+       AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+@@ -1089,7 +1089,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = {
++static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+       AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+@@ -1100,7 +1100,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = {
++static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+       AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+@@ -1111,7 +1111,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = {
++static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+       AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK,
+@@ -1122,7 +1122,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = {
++static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
+       AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+@@ -1133,7 +1133,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = {
++static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
+       AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+@@ -1144,7 +1144,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = {
++static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
+       AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+@@ -1155,7 +1155,7 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
+ };
+ 
+-static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = {
++static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
+       AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK,
+                               LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
+       AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK,
+@@ -1166,33 +1166,33 @@ static const struct airoha_pinctrl_func_
+                               LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
+ };
+ 
+-static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = {
++static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+       PINCTRL_FUNC_DESC("pon", pon),
+       PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+       PINCTRL_FUNC_DESC("sipo", sipo),
+-      PINCTRL_FUNC_DESC("mdio", an7583_mdio),
++      PINCTRL_FUNC_DESC("mdio", mdio),
+       PINCTRL_FUNC_DESC("uart", uart),
+-      PINCTRL_FUNC_DESC("i2c", an7583_i2c),
++      PINCTRL_FUNC_DESC("i2c", i2c),
+       PINCTRL_FUNC_DESC("jtag", jtag),
+       PINCTRL_FUNC_DESC("pcm", pcm),
+       PINCTRL_FUNC_DESC("spi", spi),
+-      PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
++      PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
+       PINCTRL_FUNC_DESC("emmc", emmc),
+       PINCTRL_FUNC_DESC("pnand", pnand),
+-      PINCTRL_FUNC_DESC("gpio", an7583_gpio),
+-      PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
+-      PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+-      PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0),
+-      PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0),
+-      PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0),
+-      PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0),
+-      PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1),
+-      PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1),
+-      PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1),
+-      PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1),
++      PINCTRL_FUNC_DESC("gpio", gpio),
++      PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
++      PINCTRL_FUNC_DESC("pwm", pwm),
++      PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
++      PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
++      PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
++      PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
++      PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
++      PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
++      PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
++      PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
+ };
+ 
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
+       PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)),
+       PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)),
+       PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)),
+@@ -1234,8 +1234,8 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)),
+       PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
+       PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK),
+       PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
+       PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
+       PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
+@@ -1244,11 +1244,11 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
+       PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
+       PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
+       PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)),
+       PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)),
+       PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)),
+@@ -1290,8 +1290,8 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)),
+       PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
+       PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK),
+       PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
+       PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
+       PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
+@@ -1300,11 +1300,11 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
+       PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
+       PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
+       PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)),
+       PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)),
+       PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)),
+@@ -1346,8 +1346,8 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)),
+       PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
+       PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK),
+       PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
+       PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
+       PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
+@@ -1356,11 +1356,11 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
+       PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
+       PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
+       PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)),
+       PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)),
+       PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)),
+@@ -1402,8 +1402,8 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)),
+       PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
+       PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
+-      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK),
+-      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK),
++      PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK),
+       PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
+       PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
+       PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
+@@ -1412,50 +1412,50 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
+       PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
+       PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+-      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK),
+-      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK),
++      PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK),
++      PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
++static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = {
+       PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
+       PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ };
+ 
+-static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = {
++static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+       .pinctrl_name = KBUILD_MODNAME,
+       .pinctrl_owner = THIS_MODULE,
+-      .pins = an7583_pinctrl_pins,
+-      .num_pins = ARRAY_SIZE(an7583_pinctrl_pins),
+-      .grps = an7583_pinctrl_groups,
+-      .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
+-      .funcs = an7583_pinctrl_funcs,
+-      .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
++      .pins = pinctrl_pins,
++      .num_pins = ARRAY_SIZE(pinctrl_pins),
++      .grps = pinctrl_groups,
++      .num_grps = ARRAY_SIZE(pinctrl_groups),
++      .funcs = pinctrl_funcs,
++      .num_funcs = ARRAY_SIZE(pinctrl_funcs),
+       .confs_info = {
+               [AIROHA_PINCTRL_CONFS_PULLUP] = {
+-                      .confs = an7583_pinctrl_pullup_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf),
++                      .confs = pinctrl_pullup_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
+-                      .confs = an7583_pinctrl_pulldown_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf),
++                      .confs = pinctrl_pulldown_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
+-                      .confs = an7583_pinctrl_drive_e2_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf),
++                      .confs = pinctrl_drive_e2_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
+-                      .confs = an7583_pinctrl_drive_e4_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf),
++                      .confs = pinctrl_drive_e4_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
+               },
+               [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = {
+-                      .confs = an7583_pinctrl_pcie_rst_od_conf,
+-                      .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf),
++                      .confs = pinctrl_pcie_rst_od_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf),
+               },
+       },
+ };
+ 
+ static const struct of_device_id airoha_pinctrl_of_match[] = {
+-      { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data },
++      { .compatible = "airoha,an7583-pinctrl", .data = &pinctrl_match_data },
+       { /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);

diff --git a/target/linux/airoha/patches-6.18/202-23-v7.3-pinctrl-airoha-an7583-rename-registers-to-match-.patch b/target/linux/airoha/patches-6.18/202-23-v7.3-pinctrl-airoha-an7583-rename-registers-to-match-.patch
new file mode 100644 (file)
index 0000000..399f3bd
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-23-v7.3-pinctrl-airoha-an7583-rename-registers-to-match-.patch
@@ -0,0 +1,64 @@
+From 74b966fd3b3527fa9ab18bea87c1967c56712bf5 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Mon, 22 Jun 2026 14:01:14 +0300
+Subject: [PATCH v11 28/37] pinctrl: airoha: an7583: rename registers to match
+ its an7583 names
+
+In the an7581 case the register at 0x1FA20214 is called
+RG_GPIO_2ND_I2C_MODE. The same register in the an7583 case is called
+RG_SW_TOD_1PPS_MODE.
+
+Let's rename this register to avoid potential confuse.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -8,7 +8,7 @@
+ #include "airoha-common.h"
+ 
+ /* MUX */
+-#define REG_GPIO_2ND_I2C_MODE                 0x0214
++#define REG_SW_TOD_1PPS_MODE                  0x0214
+ #define GPIO_LAN3_LED1_MODE_MASK              BIT(10)
+ #define GPIO_LAN3_LED0_MODE_MASK              BIT(9)
+ #define GPIO_LAN2_LED1_MODE_MASK              BIT(8)
+@@ -302,7 +302,7 @@
+               .name = (gpio),                                         \
+               .regmap[0] = {                                          \
+                       AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
++                      REG_SW_TOD_1PPS_MODE,                           \
+                       (mux_val),                                      \
+                       (mux_val),                                      \
+               },                                                      \
+@@ -320,7 +320,7 @@
+               .name = (gpio),                                         \
+               .regmap[0] = {                                          \
+                       AIROHA_FUNC_MUX,                                \
+-                      REG_GPIO_2ND_I2C_MODE,                          \
++                      REG_SW_TOD_1PPS_MODE,                           \
+                       (mux_val),                                      \
+                       (mux_val),                                      \
+               },                                                      \
+@@ -643,7 +643,7 @@ static const struct airoha_pinctrl_func_
+               .name = "pon_tod_1pps",
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
++                      REG_SW_TOD_1PPS_MODE,
+                       PON_TOD_1PPS_MODE_MASK,
+                       PON_TOD_1PPS_MODE_MASK
+               },
+@@ -652,7 +652,7 @@ static const struct airoha_pinctrl_func_
+               .name = "gsw_tod_1pps",
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+-                      REG_GPIO_2ND_I2C_MODE,
++                      REG_SW_TOD_1PPS_MODE,
+                       GSW_TOD_1PPS_MODE_MASK,
+                       GSW_TOD_1PPS_MODE_MASK
+               },

diff --git a/target/linux/airoha/patches-6.18/202-24-v7.3-pinctrl-airoha-an7583-add-support-for-npu_uart-p.patch b/target/linux/airoha/patches-6.18/202-24-v7.3-pinctrl-airoha-an7583-add-support-for-npu_uart-p.patch
new file mode 100644 (file)
index 0000000..86a354b
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-24-v7.3-pinctrl-airoha-an7583-add-support-for-npu_uart-p.patch
@@ -0,0 +1,48 @@
+From 4daadd3310beba5fc8442cb7829f27cbb25edada Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Tue, 16 Jun 2026 05:52:14 +0300
+Subject: [PATCH v11 30/37] pinctrl: airoha: an7583: add support for npu_uart
+ pinmux
+
+Add support for uart pin function for npu_uart pin group.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -68,6 +68,7 @@
+ #define REG_NPU_UART_EN                               0x0224
+ #define JTAG_UDI_EN_MASK                      BIT(4)
+ #define JTAG_DFD_EN_MASK                      BIT(3)
++#define NPU_UART_EN_MASK                      BIT(2)
+ 
+ #define REG_FORCE_GPIO_EN                     0x0228
+ #define FORCE_GPIO_EN(n)                      BIT(n)
+@@ -571,7 +572,7 @@ static const char *const sipo_groups[] =
+ static const char *const mdio_groups[] = { "mdio" };
+ static const char *const uart_groups[] = {
+       "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts",
+-      "uart4", "uart5"
++      "uart4", "uart5", "npu_uart"
+ };
+ static const char *const i2c_groups[] = { "i2c0", "i2c1" };
+ static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
+@@ -751,6 +752,15 @@ static const struct airoha_pinctrl_func_
+                       GPIO_UART5_MODE_MASK
+               },
+               .regmap_size = 1,
++      }, {
++              .name = "npu_uart",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      NPU_UART_EN_MASK,
++                      NPU_UART_EN_MASK
++              },
++              .regmap_size = 1,
+       },
+ };
+ 

diff --git a/target/linux/airoha/patches-6.18/202-25-v7.3-pinctrl-airoha-an7583-add-support-for-pon_alt-pi.patch b/target/linux/airoha/patches-6.18/202-25-v7.3-pinctrl-airoha-an7583-add-support-for-pon_alt-pi.patch
new file mode 100644 (file)
index 0000000..d151245
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-25-v7.3-pinctrl-airoha-an7583-add-support-for-pon_alt-pi.patch
@@ -0,0 +1,69 @@
+From 23eb3c2b54c9dc4be10936e8bf86844b9886b507 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Tue, 16 Jun 2026 06:05:25 +0300
+Subject: [PATCH v11 31/37] pinctrl: airoha: an7583: add support for pon_alt
+ pinmux
+
+Add support for pon pin function for pon_alt pin group.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 16 ++++++++++++++--
+ 1 file changed, 14 insertions(+), 2 deletions(-)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -38,6 +38,7 @@
+ #define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
+ 
+ #define REG_GPIO_PON_MODE                     0x021c
++#define GPIO_PON_ALT_MODE_MASK                        BIT(27)
+ #define MDIO_0_GPIO_MODE_MASK                 BIT(26)
+ #define MDC_0_GPIO_MODE_MASK                  BIT(25)
+ #define UART_RXD_GPIO_MODE_MASK                       BIT(24)
+@@ -391,6 +392,7 @@ static struct pinctrl_pin_desc pinctrl_p
+ };
+ 
+ static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
++static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
+ static const int pon_tod_1pps_pins[] = { 32 };
+ static const int gsw_tod_1pps_pins[] = { 32 };
+ static const int sipo_pins[] = { 34, 35 };
+@@ -480,6 +482,7 @@ static const int pcie_reset1_pins[] = {
+ 
+ static const struct pingroup pinctrl_groups[] = {
+       PINCTRL_PIN_GROUP("pon", pon),
++      PINCTRL_PIN_GROUP("pon_alt", pon_alt),
+       PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+       PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+       PINCTRL_PIN_GROUP("sipo", sipo),
+@@ -564,7 +567,7 @@ static const struct pingroup pinctrl_gro
+       PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
+ };
+ 
+-static const char *const pon_groups[] = { "pon" };
++static const char *const pon_groups[] = { "pon", "pon_alt" };
+ static const char *const tod_1pps_groups[] = {
+       "pon_tod_1pps", "gsw_tod_1pps"
+ };
+@@ -632,10 +635,19 @@ static const struct airoha_pinctrl_func_
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+-                      GPIO_PON_MODE_MASK,
++                      GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
+                       GPIO_PON_MODE_MASK
+               },
+               .regmap_size = 1,
++      }, {
++              .name = "pon_alt",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK,
++                      GPIO_PON_ALT_MODE_MASK
++              },
++              .regmap_size = 1,
+       },
+ };
+ 

diff --git a/target/linux/airoha/patches-6.18/202-26-v7.3-pinctrl-airoha-an7583-add-support-for-olt-pinmux.patch b/target/linux/airoha/patches-6.18/202-26-v7.3-pinctrl-airoha-an7583-add-support-for-olt-pinmux.patch
new file mode 100644 (file)
index 0000000..3a033fd
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-26-v7.3-pinctrl-airoha-an7583-add-support-for-olt-pinmux.patch
@@ -0,0 +1,74 @@
+From c5fa73c4bf0a0c5a381f9634080f6d7b6f2e8e37 Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Wed, 17 Jun 2026 07:04:40 +0300
+Subject: [PATCH v11 32/37] pinctrl: airoha: an7583: add support for olt pinmux
+
+Add support for olt pin function for olt pin group.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 18 ++++++++++++++++++
+ 1 file changed, 18 insertions(+)
+
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -53,6 +53,7 @@
+ #define I2C0_SCL_GPIO_MODE_MASK                       BIT(15)
+ #define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
+ #define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
++#define GPIO_OLT_MODE_MASK                    BIT(12)
+ #define SIPO_RCLK_MODE_MASK                   BIT(11)
+ #define GPIO_PCIE_RESET1_MASK                 BIT(10)
+ #define GPIO_PCIE_RESET0_MASK                 BIT(9)
+@@ -393,6 +394,7 @@ static struct pinctrl_pin_desc pinctrl_p
+ 
+ static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 };
+ static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 };
++static const int olt_pins[] = { 36, 37, 38, 39, 40 };
+ static const int pon_tod_1pps_pins[] = { 32 };
+ static const int gsw_tod_1pps_pins[] = { 32 };
+ static const int sipo_pins[] = { 34, 35 };
+@@ -483,6 +485,7 @@ static const int pcie_reset1_pins[] = {
+ static const struct pingroup pinctrl_groups[] = {
+       PINCTRL_PIN_GROUP("pon", pon),
+       PINCTRL_PIN_GROUP("pon_alt", pon_alt),
++      PINCTRL_PIN_GROUP("olt", olt),
+       PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
+       PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
+       PINCTRL_PIN_GROUP("sipo", sipo),
+@@ -568,6 +571,7 @@ static const struct pingroup pinctrl_gro
+ };
+ 
+ static const char *const pon_groups[] = { "pon", "pon_alt" };
++static const char *const olt_groups[] = { "olt" };
+ static const char *const tod_1pps_groups[] = {
+       "pon_tod_1pps", "gsw_tod_1pps"
+ };
+@@ -651,6 +655,19 @@ static const struct airoha_pinctrl_func_
+       },
+ };
+ 
++static const struct airoha_pinctrl_func_group olt_func_group[] = {
++      {
++              .name = "olt",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_OLT_MODE_MASK,
++                      GPIO_OLT_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
+ static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
+       {
+               .name = "pon_tod_1pps",
+@@ -1190,6 +1207,7 @@ static const struct airoha_pinctrl_func_
+ 
+ static const struct airoha_pinctrl_func pinctrl_funcs[] = {
+       PINCTRL_FUNC_DESC("pon", pon),
++      PINCTRL_FUNC_DESC("olt", olt),
+       PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
+       PINCTRL_FUNC_DESC("sipo", sipo),
+       PINCTRL_FUNC_DESC("mdio", mdio),

diff --git a/target/linux/airoha/patches-6.18/202-27-v7.3-pinctrl-airoha-add-support-of-en7523-SoC.patch b/target/linux/airoha/patches-6.18/202-27-v7.3-pinctrl-airoha-add-support-of-en7523-SoC.patch
new file mode 100644 (file)
index 0000000..496a61f
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-27-v7.3-pinctrl-airoha-add-support-of-en7523-SoC.patch
@@ -0,0 +1,1204 @@
+From a32e1f15d5a5dde4bd80d0b4eb87220ce14120ae Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Tue, 16 Jun 2026 04:47:17 +0300
+Subject: [PATCH v11 34/37] pinctrl: airoha: add support of en7523 SoC
+
+This patch adds support of Airoha en7523 SoC pin controller.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/Kconfig          |    9 +
+ drivers/pinctrl/airoha/Makefile         |    1 +
+ drivers/pinctrl/airoha/pinctrl-en7523.c | 1156 +++++++++++++++++++++++
+ 3 files changed, 1166 insertions(+)
+ create mode 100644 drivers/pinctrl/airoha/pinctrl-en7523.c
+
+--- a/drivers/pinctrl/airoha/Kconfig
++++ b/drivers/pinctrl/airoha/Kconfig
+@@ -15,6 +15,7 @@ config PINCTRL_AIROHA
+       select REGMAP_MMIO
+       imply PINCTRL_AIROHA_AN7581
+       imply PINCTRL_AIROHA_AN7583
++      imply PINCTRL_AIROHA_EN7523
+       help
+         Shared pin controller and gpio driver code for different
+         Airoha SoCs.
+@@ -35,4 +36,12 @@ config PINCTRL_AIROHA_AN7583
+         Say yes here to support pin controller and gpio driver
+         on Airoha AN7583, AN7553, AN7567 and other compatible SoCs.
+ 
++config PINCTRL_AIROHA_EN7523
++      tristate "EN7523 pinctrl"
++      depends on ARM || COMPILE_TEST
++      depends on PINCTRL_AIROHA
++      help
++        Say yes here to support pin controller and gpio driver
++        on Airoha EN7523, EN7529, EN7562 and other compatible SoCs.
++
+ endmenu
+--- a/drivers/pinctrl/airoha/Makefile
++++ b/drivers/pinctrl/airoha/Makefile
+@@ -6,3 +6,4 @@ obj-$(CONFIG_PINCTRL_AIROHA)           += pinctrl
+ # SoC drivers
+ obj-$(CONFIG_PINCTRL_AIROHA_AN7581)   += pinctrl-an7581.o
+ obj-$(CONFIG_PINCTRL_AIROHA_AN7583)   += pinctrl-an7583.o
++obj-$(CONFIG_PINCTRL_AIROHA_EN7523)   += pinctrl-en7523.o
+--- /dev/null
++++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
+@@ -0,0 +1,1156 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Author: Lorenzo Bianconi <lorenzo@kernel.org>
++ * Author: Benjamin Larsson <benjamin.larsson@genexis.eu>
++ * Author: Markus Gothe <markus.gothe@genexis.eu>
++ * Author: Matheus Sampaio Queiroga <srherobrine20@gmail.com>
++ * Author: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
++ */
++#include "airoha-common.h"
++
++/* MUX */
++#define REG_GPIO_2ND_I2C_MODE                 0x0210
++#define GPIO_I2S_MODE_MASK                    BIT(12)
++#define GPIO_I2C_SLAVE_MODE_MODE              BIT(11)
++#define GPIO_LAN3_LED1_MODE_MASK              BIT(10)
++#define GPIO_LAN3_LED0_MODE_MASK              BIT(9)
++#define GPIO_LAN2_LED1_MODE_MASK              BIT(8)
++#define GPIO_LAN2_LED0_MODE_MASK              BIT(7)
++#define GPIO_LAN1_LED1_MODE_MASK              BIT(6)
++#define GPIO_LAN1_LED0_MODE_MASK              BIT(5)
++#define GPIO_LAN0_LED1_MODE_MASK              BIT(4)
++#define GPIO_LAN0_LED0_MODE_MASK              BIT(3)
++#define PON_TOD_1PPS_MODE_MASK                        BIT(2)
++#define GSW_TOD_1PPS_MODE_MASK                        BIT(1)
++#define GPIO_2ND_I2C_MODE_MASK                        BIT(0)
++
++#define REG_GPIO_SPI_CS1_MODE                 0x0214
++#define GPIO_PCM_SPI_CS4_MODE_MASK            BIT(21)
++#define GPIO_PCM_SPI_CS3_MODE_MASK            BIT(20)
++#define GPIO_PCM_SPI_CS2_MODE_P156_MASK               BIT(19)
++#define GPIO_PCM_SPI_CS2_MODE_P128_MASK               BIT(18)
++#define GPIO_PCM_SPI_CS1_MODE_MASK            BIT(17)
++#define GPIO_PCM_SPI_MODE_MASK                        BIT(16)
++#define GPIO_PCM2_MODE_MASK                   BIT(13)
++#define GPIO_PCM1_MODE_MASK                   BIT(12)
++#define GPIO_PCM_INT_MODE_MASK                        BIT(9)
++#define GPIO_PCM_RESET_MODE_MASK              BIT(8)
++#define GPIO_SPI_QUAD_MODE_MASK                       BIT(4)
++#define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
++
++#define REG_GPIO_PON_MODE                     0x0218
++#define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
++#define SIPO_RCLK_MODE_MASK                   BIT(11)
++#define GPIO_PCIE_RESET1_MASK                 BIT(10)
++#define GPIO_PCIE_RESET0_MASK                 BIT(9)
++#define GPIO_UART2_MODE_MASK                  BIT(3)
++#define GPIO_SIPO_MODE_MASK                   BIT(2)
++#define GPIO_PON_MODE_MASK                    BIT(0)
++
++#define REG_NPU_UART_EN                               0x0220
++#define JTAG_UDI_EN_MASK                      BIT(4)
++#define JTAG_DFD_EN_MASK                      BIT(3)
++#define NPU_UART_EN_MASK                      BIT(2)
++
++#define REG_FORCE_GPIO_EN                     0x0224
++#define FORCE_GPIO_EN(n)                      BIT(n)
++
++/* LED MAP */
++#define REG_LAN_LED0_MAPPING                  0x0278
++#define REG_LAN_LED1_MAPPING                  0x027c
++
++#define LAN3_LED_MAPPING_MASK                 GENMASK(14, 12)
++#define LAN3_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n))
++
++#define LAN2_LED_MAPPING_MASK                 GENMASK(10, 8)
++#define LAN2_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n))
++
++#define LAN1_LED_MAPPING_MASK                 GENMASK(6, 4)
++#define LAN1_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n))
++
++#define LAN0_LED_MAPPING_MASK                 GENMASK(2, 0)
++#define LAN0_PHY_LED_MAP(_n)                  FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n))
++
++/* CONF */
++#define REG_I2C_SDA_E2                                0x001c
++#define SPI_MISO_E2_MASK                      BIT(13)
++#define SPI_MOSI_E2_MASK                      BIT(12)
++#define SPI_CLK_E2_MASK                               BIT(11)
++#define SPI_CS0_E2_MASK                               BIT(10)
++#define PCIE1_RESET_E2_MASK                   BIT(9)
++#define PCIE0_RESET_E2_MASK                   BIT(8)
++#define UART1_RXD_E2_MASK                     BIT(3)
++#define UART1_TXD_E2_MASK                     BIT(2)
++#define I2C_SCL_E2_MASK                               BIT(1)
++#define I2C_SDA_E2_MASK                               BIT(0)
++
++#define REG_I2C_SDA_E4                                0x0020
++#define SPI_MISO_E4_MASK                      BIT(13)
++#define SPI_MOSI_E4_MASK                      BIT(12)
++#define SPI_CLK_E4_MASK                               BIT(11)
++#define SPI_CS0_E4_MASK                               BIT(10)
++#define PCIE1_RESET_E4_MASK                   BIT(9)
++#define PCIE0_RESET_E4_MASK                   BIT(8)
++#define UART1_RXD_E4_MASK                     BIT(3)
++#define UART1_TXD_E4_MASK                     BIT(2)
++#define I2C_SCL_E4_MASK                               BIT(1)
++#define I2C_SDA_E4_MASK                               BIT(0)
++
++#define REG_GPIO_L_E2                         0x0024
++#define REG_GPIO_L_E4                         0x0028
++
++#define REG_I2C_SDA_PU                                0x0044
++#define SPI_MISO_PU_MASK                      BIT(13)
++#define SPI_MOSI_PU_MASK                      BIT(12)
++#define SPI_CLK_PU_MASK                               BIT(11)
++#define SPI_CS0_PU_MASK                               BIT(10)
++#define PCIE1_RESET_PU_MASK                   BIT(9)
++#define PCIE0_RESET_PU_MASK                   BIT(8)
++#define UART1_RXD_PU_MASK                     BIT(3)
++#define UART1_TXD_PU_MASK                     BIT(2)
++#define I2C_SCL_PU_MASK                               BIT(1)
++#define I2C_SDA_PU_MASK                               BIT(0)
++
++#define REG_I2C_SDA_PD                                0x0048
++#define SPI_MISO_PD_MASK                      BIT(13)
++#define SPI_MOSI_PD_MASK                      BIT(12)
++#define SPI_CLK_PD_MASK                               BIT(11)
++#define SPI_CS0_PD_MASK                               BIT(10)
++#define PCIE1_RESET_PD_MASK                   BIT(9)
++#define PCIE0_RESET_PD_MASK                   BIT(8)
++#define UART1_RXD_PD_MASK                     BIT(3)
++#define UART1_TXD_PD_MASK                     BIT(2)
++#define I2C_SCL_PD_MASK                               BIT(1)
++#define I2C_SDA_PD_MASK                               BIT(0)
++
++#define REG_GPIO_L_PU                         0x004c
++#define REG_GPIO_L_PD                         0x0050
++
++/* PWM MODE CONF */
++#define REG_GPIO_FLASH_MODE_CFG                       0x0034
++#define GPIO15_FLASH_MODE_CFG                 BIT(15)
++#define GPIO14_FLASH_MODE_CFG                 BIT(14)
++#define GPIO13_FLASH_MODE_CFG                 BIT(13)
++#define GPIO12_FLASH_MODE_CFG                 BIT(12)
++#define GPIO11_FLASH_MODE_CFG                 BIT(11)
++#define GPIO10_FLASH_MODE_CFG                 BIT(10)
++#define GPIO9_FLASH_MODE_CFG                  BIT(9)
++#define GPIO8_FLASH_MODE_CFG                  BIT(8)
++#define GPIO7_FLASH_MODE_CFG                  BIT(7)
++#define GPIO6_FLASH_MODE_CFG                  BIT(6)
++#define GPIO5_FLASH_MODE_CFG                  BIT(5)
++#define GPIO4_FLASH_MODE_CFG                  BIT(4)
++#define GPIO3_FLASH_MODE_CFG                  BIT(3)
++#define GPIO2_FLASH_MODE_CFG                  BIT(2)
++#define GPIO1_FLASH_MODE_CFG                  BIT(1)
++#define GPIO0_FLASH_MODE_CFG                  BIT(0)
++
++/* PWM MODE CONF EXT */
++#define REG_GPIO_FLASH_MODE_CFG_EXT           0x0068
++#define GPIO51_FLASH_MODE_CFG                 BIT(31)
++#define GPIO50_FLASH_MODE_CFG                 BIT(30)
++#define GPIO49_FLASH_MODE_CFG                 BIT(29)
++#define GPIO48_FLASH_MODE_CFG                 BIT(28)
++#define GPIO47_FLASH_MODE_CFG                 BIT(27)
++#define GPIO46_FLASH_MODE_CFG                 BIT(26)
++#define GPIO45_FLASH_MODE_CFG                 BIT(25)
++#define GPIO44_FLASH_MODE_CFG                 BIT(24)
++#define GPIO43_FLASH_MODE_CFG                 BIT(23)
++#define GPIO42_FLASH_MODE_CFG                 BIT(22)
++#define GPIO41_FLASH_MODE_CFG                 BIT(21)
++#define GPIO40_FLASH_MODE_CFG                 BIT(20)
++#define GPIO39_FLASH_MODE_CFG                 BIT(19)
++#define GPIO38_FLASH_MODE_CFG                 BIT(18)
++#define GPIO37_FLASH_MODE_CFG                 BIT(17)
++#define GPIO36_FLASH_MODE_CFG                 BIT(16)
++#define GPIO31_FLASH_MODE_CFG                 BIT(15)
++#define GPIO30_FLASH_MODE_CFG                 BIT(14)
++#define GPIO29_FLASH_MODE_CFG                 BIT(13)
++#define GPIO28_FLASH_MODE_CFG                 BIT(12)
++#define GPIO27_FLASH_MODE_CFG                 BIT(11)
++#define GPIO26_FLASH_MODE_CFG                 BIT(10)
++#define GPIO25_FLASH_MODE_CFG                 BIT(9)
++#define GPIO24_FLASH_MODE_CFG                 BIT(8)
++#define GPIO23_FLASH_MODE_CFG                 BIT(7)
++#define GPIO22_FLASH_MODE_CFG                 BIT(6)
++#define GPIO21_FLASH_MODE_CFG                 BIT(5)
++#define GPIO20_FLASH_MODE_CFG                 BIT(4)
++#define GPIO19_FLASH_MODE_CFG                 BIT(3)
++#define GPIO18_FLASH_MODE_CFG                 BIT(2)
++#define GPIO17_FLASH_MODE_CFG                 BIT(1)
++#define GPIO16_FLASH_MODE_CFG                 BIT(0)
++
++#define AIROHA_PINCTRL_GPIO(gpio, mux_val)                    \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val)      \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      0                                       \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++/* PWM */
++#define AIROHA_PINCTRL_PWM(gpio, mux_val)                     \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_MUX,                    \
++                      REG_GPIO_FLASH_MODE_CFG,                \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val)                 \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap_size = 1,                               \
++      }
++
++#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val)   \
++      {                                                       \
++              .name = (gpio),                                 \
++              .regmap[0] = {                                  \
++                      AIROHA_FUNC_PWM_EXT_MUX,                \
++                      REG_GPIO_FLASH_MODE_CFG_EXT,            \
++                      (mux_val),                              \
++                      (mux_val)                               \
++              },                                              \
++              .regmap[1] = {                                  \
++                      AIROHA_FUNC_MUX,                        \
++                      REG_GPIO_PON_MODE,                      \
++                      (smux_val),                             \
++                      (smux_val)                              \
++              },                                              \
++              .regmap_size = 2,                               \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED0_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val)     \
++      {                                                               \
++              .name = (gpio),                                         \
++              .regmap[0] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_GPIO_2ND_I2C_MODE,                          \
++                      (mux_val),                                      \
++                      (mux_val),                                      \
++              },                                                      \
++              .regmap[1] = {                                          \
++                      AIROHA_FUNC_MUX,                                \
++                      REG_LAN_LED1_MAPPING,                           \
++                      (map_mask),                                     \
++                      (map_val),                                      \
++              },                                                      \
++              .regmap_size = 2,                                       \
++      }
++
++static struct pinctrl_pin_desc pinctrl_pins[] = {
++      PINCTRL_PIN(2, "i2c_sda"),
++      PINCTRL_PIN(3, "i2c_scl"),
++      PINCTRL_PIN(4, "spi_cs0"),
++      PINCTRL_PIN(5, "spi_clk"),
++      PINCTRL_PIN(6, "spi_mosi"),
++      PINCTRL_PIN(7, "spi_miso"),
++      PINCTRL_PIN(8, "uart1_txd"),
++      PINCTRL_PIN(9, "uart1_rxd"),
++      PINCTRL_PIN(12, "gpio0"),
++      PINCTRL_PIN(13, "gpio1"),
++      PINCTRL_PIN(14, "gpio2"),
++      PINCTRL_PIN(15, "gpio3"),
++      PINCTRL_PIN(16, "gpio4"),
++      PINCTRL_PIN(17, "gpio5"),
++      PINCTRL_PIN(18, "gpio6"),
++      PINCTRL_PIN(19, "gpio7"),
++      PINCTRL_PIN(20, "gpio8"),
++      PINCTRL_PIN(21, "gpio9"),
++      PINCTRL_PIN(22, "gpio10"),
++      PINCTRL_PIN(23, "gpio11"),
++      PINCTRL_PIN(24, "gpio12"),
++      PINCTRL_PIN(25, "gpio13"),
++      PINCTRL_PIN(26, "gpio14"),
++      PINCTRL_PIN(27, "gpio15"),
++      PINCTRL_PIN(28, "gpio16"),
++      PINCTRL_PIN(29, "gpio17"),
++      PINCTRL_PIN(30, "gpio18"),
++      PINCTRL_PIN(31, "gpio19"),
++      PINCTRL_PIN(32, "gpio20"),
++      PINCTRL_PIN(33, "gpio21"),
++      PINCTRL_PIN(34, "gpio22"),
++      PINCTRL_PIN(35, "gpio23"),
++      PINCTRL_PIN(36, "gpio24"),
++      PINCTRL_PIN(37, "gpio25"),
++      PINCTRL_PIN(38, "gpio26"),
++      PINCTRL_PIN(39, "gpio27"),
++      PINCTRL_PIN(40, "pcie_reset0"),
++      PINCTRL_PIN(41, "pcie_reset1"),
++};
++
++static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 };
++static const int pon_tod_1pps_pins[] = { 21 };
++static const int gsw_tod_1pps_pins[] = { 21 };
++static const int sipo_pins[] = { 13, 38 };
++static const int sipo_rclk_pins[] = { 13, 30, 38 };
++static const int mdio_pins[] = { 20, 21 };
++static const int uart2_pins[] = { 20, 21 };
++static const int npu_uart_pins[] = { 13, 38 };
++static const int i2c0_pins[] = { 2, 3 };
++static const int i2c1_pins[] = { 14, 15 };
++static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 };
++static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 };
++static const int i2s_pins[] = { 16, 17, 18, 19 };
++static const int pcm1_pins[] = { 24, 25, 26, 27 };
++static const int pcm2_pins[] = { 16, 17, 18, 19 };
++static const int spi_pins[] = { 4, 5, 6, 7 };
++static const int spi_quad_pins[] = { 14, 15 };
++static const int spi_cs1_pins[] = { 21 };
++static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 };
++static const int pcm_spi_int_pins[] = { 15 };
++static const int pcm_spi_rst_pins[] = { 14 };
++static const int pcm_spi_cs1_pins[] = { 22 };
++static const int pcm_spi_cs2_p128_pins[] = { 39 };
++static const int pcm_spi_cs2_p156_pins[] = { 39 };
++static const int pcm_spi_cs3_pins[] = { 20 };
++static const int pcm_spi_cs4_pins[] = { 23 };
++static const int gpio0_pins[] = { 12 };
++static const int gpio1_pins[] = { 13 };
++static const int gpio2_pins[] = { 14 };
++static const int gpio3_pins[] = { 15 };
++static const int gpio4_pins[] = { 16 };
++static const int gpio5_pins[] = { 17 };
++static const int gpio6_pins[] = { 18 };
++static const int gpio7_pins[] = { 19 };
++static const int gpio8_pins[] = { 20 };
++static const int gpio9_pins[] = { 21 };
++static const int gpio10_pins[] = { 22 };
++static const int gpio11_pins[] = { 23 };
++static const int gpio12_pins[] = { 24 };
++static const int gpio13_pins[] = { 25 };
++static const int gpio14_pins[] = { 26 };
++static const int gpio15_pins[] = { 27 };
++static const int gpio16_pins[] = { 28 };
++static const int gpio17_pins[] = { 29 };
++static const int gpio18_pins[] = { 30 };
++static const int gpio19_pins[] = { 31 };
++static const int gpio20_pins[] = { 32 };
++static const int gpio21_pins[] = { 33 };
++static const int gpio22_pins[] = { 34 };
++static const int gpio23_pins[] = { 35 };
++static const int gpio24_pins[] = { 36 };
++static const int gpio25_pins[] = { 37 };
++static const int gpio26_pins[] = { 38 };
++static const int gpio27_pins[] = { 39 };
++static const int gpio28_pins[] = { 40 };
++static const int gpio29_pins[] = { 41 };
++static const int pcie_reset0_pins[] = { 40 };
++static const int pcie_reset1_pins[] = { 41 };
++
++static const struct pingroup pinctrl_groups[] = {
++      PINCTRL_PIN_GROUP("pon", pon),
++      PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps),
++      PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps),
++      PINCTRL_PIN_GROUP("sipo", sipo),
++      PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk),
++      PINCTRL_PIN_GROUP("mdio", mdio),
++      PINCTRL_PIN_GROUP("uart2", uart2),
++      PINCTRL_PIN_GROUP("npu_uart", npu_uart),
++      PINCTRL_PIN_GROUP("i2c0", i2c0),
++      PINCTRL_PIN_GROUP("i2c1", i2c1),
++      PINCTRL_PIN_GROUP("jtag_udi", jtag_udi),
++      PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd),
++      PINCTRL_PIN_GROUP("i2s", i2s),
++      PINCTRL_PIN_GROUP("pcm1", pcm1),
++      PINCTRL_PIN_GROUP("pcm2", pcm2),
++      PINCTRL_PIN_GROUP("spi", spi),
++      PINCTRL_PIN_GROUP("spi_quad", spi_quad),
++      PINCTRL_PIN_GROUP("spi_cs1", spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi", pcm_spi),
++      PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int),
++      PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst),
++      PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128),
++      PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156),
++      PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3),
++      PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4),
++      PINCTRL_PIN_GROUP("gpio0", gpio0),
++      PINCTRL_PIN_GROUP("gpio1", gpio1),
++      PINCTRL_PIN_GROUP("gpio2", gpio2),
++      PINCTRL_PIN_GROUP("gpio3", gpio3),
++      PINCTRL_PIN_GROUP("gpio4", gpio4),
++      PINCTRL_PIN_GROUP("gpio5", gpio5),
++      PINCTRL_PIN_GROUP("gpio6", gpio6),
++      PINCTRL_PIN_GROUP("gpio7", gpio7),
++      PINCTRL_PIN_GROUP("gpio8", gpio8),
++      PINCTRL_PIN_GROUP("gpio9", gpio9),
++      PINCTRL_PIN_GROUP("gpio10", gpio10),
++      PINCTRL_PIN_GROUP("gpio11", gpio11),
++      PINCTRL_PIN_GROUP("gpio12", gpio12),
++      PINCTRL_PIN_GROUP("gpio13", gpio13),
++      PINCTRL_PIN_GROUP("gpio14", gpio14),
++      PINCTRL_PIN_GROUP("gpio15", gpio15),
++      PINCTRL_PIN_GROUP("gpio16", gpio16),
++      PINCTRL_PIN_GROUP("gpio17", gpio17),
++      PINCTRL_PIN_GROUP("gpio18", gpio18),
++      PINCTRL_PIN_GROUP("gpio19", gpio19),
++      PINCTRL_PIN_GROUP("gpio20", gpio20),
++      PINCTRL_PIN_GROUP("gpio21", gpio21),
++      PINCTRL_PIN_GROUP("gpio22", gpio22),
++      PINCTRL_PIN_GROUP("gpio23", gpio23),
++      PINCTRL_PIN_GROUP("gpio24", gpio24),
++      PINCTRL_PIN_GROUP("gpio25", gpio25),
++      PINCTRL_PIN_GROUP("gpio26", gpio26),
++      PINCTRL_PIN_GROUP("gpio27", gpio27),
++      PINCTRL_PIN_GROUP("gpio28", gpio28),
++      PINCTRL_PIN_GROUP("gpio29", gpio29),
++      PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0),
++      PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1),
++};
++
++static const char *const pon_groups[] = { "pon" };
++static const char *const tod_1pps_groups[] = {
++      "pon_tod_1pps", "gsw_tod_1pps"
++};
++static const char *const sipo_groups[] = { "sipo", "sipo_rclk" };
++static const char *const mdio_groups[] = { "mdio" };
++static const char *const uart_groups[] = { "uart2", "npu_uart" };
++static const char *const i2c_groups[] = { "i2c1" };
++static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
++static const char *const pcm_groups[] = { "pcm1", "pcm2" };
++static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
++static const char *const pcm_spi_groups[] = {
++      "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1",
++      "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4"
++};
++static const char *const i2s_groups[] = { "i2s" };
++static const char *const gpio_groups[] = { "gpio28", "gpio29" };
++static const char *const pcie_reset_groups[] = {
++      "pcie_reset0", "pcie_reset1"
++};
++static const char *const pwm_groups[] = {
++      "gpio0",  "gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",
++      "gpio6",  "gpio7",  "gpio8",  "gpio9",  "gpio10", "gpio11",
++      "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
++      "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23",
++      "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29"
++};
++static const char *const phy1_led0_groups[] = {
++      "gpio22", "gpio23", "gpio24", "gpio25"
++};
++static const char *const phy2_led0_groups[] = {
++      "gpio22", "gpio23", "gpio24", "gpio25"
++};
++static const char *const phy3_led0_groups[] = {
++      "gpio22", "gpio23", "gpio24", "gpio25"
++};
++static const char *const phy4_led0_groups[] = {
++      "gpio22", "gpio23", "gpio24", "gpio25"
++};
++static const char *const phy1_led1_groups[] = {
++      "gpio7", "gpio6", "gpio5", "gpio4"
++};
++static const char *const phy2_led1_groups[] = {
++      "gpio7", "gpio6", "gpio5", "gpio4"
++};
++static const char *const phy3_led1_groups[] = {
++      "gpio7", "gpio6", "gpio5", "gpio4"
++};
++static const char *const phy4_led1_groups[] = {
++      "gpio7", "gpio6", "gpio5", "gpio4"
++};
++
++static const struct airoha_pinctrl_func_group pon_func_group[] = {
++      {
++              .name = "pon",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PON_MODE_MASK,
++                      GPIO_PON_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = {
++      {
++              .name = "pon_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      PON_TOD_1PPS_MODE_MASK,
++                      PON_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "gsw_tod_1pps",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GSW_TOD_1PPS_MODE_MASK,
++                      GSW_TOD_1PPS_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group sipo_func_group[] = {
++      {
++              .name = "sipo",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "sipo_rclk",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK,
++                      GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group mdio_func_group[] = {
++      {
++              .name = "mdio",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_SGMII_MDIO_MODE_MASK,
++                      GPIO_SGMII_MDIO_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group uart_func_group[] = {
++      {
++              .name = "uart2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_UART2_MODE_MASK,
++                      GPIO_UART2_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "npu_uart",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      NPU_UART_EN_MASK,
++                      NPU_UART_EN_MASK
++              },
++              .regmap_size = 1,
++      }
++};
++
++static const struct airoha_pinctrl_func_group i2c_func_group[] = {
++      {
++              .name = "i2c1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GPIO_2ND_I2C_MODE_MASK,
++                      GPIO_2ND_I2C_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group jtag_func_group[] = {
++      {
++              .name = "jtag_udi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_UDI_EN_MASK,
++                      JTAG_UDI_EN_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "jtag_dfd",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_NPU_UART_EN,
++                      JTAG_DFD_EN_MASK,
++                      JTAG_DFD_EN_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pcm_func_group[] = {
++      {
++              .name = "pcm1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM1_MODE_MASK,
++                      GPIO_PCM1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm2",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM2_MODE_MASK,
++                      GPIO_PCM2_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group spi_func_group[] = {
++      {
++              .name = "spi_quad",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_QUAD_MODE_MASK,
++                      GPIO_SPI_QUAD_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_SPI_CS1_MODE_MASK,
++                      GPIO_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
++      {
++              .name = "pcm_spi",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_MODE_MASK,
++                      GPIO_PCM_SPI_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_int",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_INT_MODE_MASK,
++                      GPIO_PCM_INT_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_rst",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_RESET_MODE_MASK,
++                      GPIO_PCM_RESET_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS1_MODE_MASK,
++                      GPIO_PCM_SPI_CS1_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs2_p128",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS2_MODE_P128_MASK,
++                      GPIO_PCM_SPI_CS2_MODE_P128_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs2_p156",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS2_MODE_P156_MASK,
++                      GPIO_PCM_SPI_CS2_MODE_P156_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs3",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS3_MODE_MASK,
++                      GPIO_PCM_SPI_CS3_MODE_MASK
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcm_spi_cs4",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_SPI_CS1_MODE,
++                      GPIO_PCM_SPI_CS4_MODE_MASK,
++                      GPIO_PCM_SPI_CS4_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group i2s_func_group[] = {
++      {
++              .name = "i2s",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_2ND_I2C_MODE,
++                      GPIO_I2S_MODE_MASK,
++                      GPIO_I2S_MODE_MASK
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group gpio_func_group[] = {
++      AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG,
++                              GPIO_PCIE_RESET1_MASK),
++};
++
++static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
++      {
++              .name = "pcie_reset0",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET0_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      }, {
++              .name = "pcie_reset1",
++              .regmap[0] = {
++                      AIROHA_FUNC_MUX,
++                      REG_GPIO_PON_MODE,
++                      GPIO_PCIE_RESET1_MASK,
++                      0
++              },
++              .regmap_size = 1,
++      },
++};
++
++static const struct airoha_pinctrl_func_group pwm_func_group[] = {
++      AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET0_MASK),
++      AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG,
++                                 GPIO_PCIE_RESET1_MASK),
++};
++
++static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
++      AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
++};
++
++static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
++      AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
++};
++
++static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
++      AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
++};
++
++static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = {
++      AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK,
++                              LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK,
++                              LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK,
++                              LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
++      AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK,
++                              LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),
++};
++
++static const struct airoha_pinctrl_func pinctrl_funcs[] = {
++      PINCTRL_FUNC_DESC("pon", pon),
++      PINCTRL_FUNC_DESC("tod_1pps", tod_1pps),
++      PINCTRL_FUNC_DESC("sipo", sipo),
++      PINCTRL_FUNC_DESC("mdio", mdio),
++      PINCTRL_FUNC_DESC("uart", uart),
++      PINCTRL_FUNC_DESC("i2c", i2c),
++      PINCTRL_FUNC_DESC("jtag", jtag),
++      PINCTRL_FUNC_DESC("pcm", pcm),
++      PINCTRL_FUNC_DESC("spi", spi),
++      PINCTRL_FUNC_DESC("pcm_spi", pcm_spi),
++      PINCTRL_FUNC_DESC("i2s", i2s),
++      PINCTRL_FUNC_DESC("gpio", gpio),
++      PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
++      PINCTRL_FUNC_DESC("pwm", pwm),
++      PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
++      PINCTRL_FUNC_DESC("phy2_led0", phy2_led0),
++      PINCTRL_FUNC_DESC("phy3_led0", phy3_led0),
++      PINCTRL_FUNC_DESC("phy4_led0", phy4_led0),
++      PINCTRL_FUNC_DESC("phy1_led1", phy1_led1),
++      PINCTRL_FUNC_DESC("phy2_led1", phy2_led1),
++      PINCTRL_FUNC_DESC("phy3_led1", phy3_led1),
++      PINCTRL_FUNC_DESC("phy4_led1", phy4_led1),
++};
++
++static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK),
++      PINCTRL_CONF_DESC(8, REG_I2C_SDA_PU, UART1_TXD_PU_MASK),
++      PINCTRL_CONF_DESC(9, REG_I2C_SDA_PU, UART1_RXD_PU_MASK),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)),
++      PINCTRL_CONF_DESC(40, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
++};
++
++static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK),
++      PINCTRL_CONF_DESC(8, REG_I2C_SDA_PD, UART1_TXD_PD_MASK),
++      PINCTRL_CONF_DESC(9, REG_I2C_SDA_PD, UART1_RXD_PD_MASK),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)),
++      PINCTRL_CONF_DESC(40, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
++};
++
++static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK),
++      PINCTRL_CONF_DESC(8, REG_I2C_SDA_E2, UART1_TXD_E2_MASK),
++      PINCTRL_CONF_DESC(9, REG_I2C_SDA_E2, UART1_RXD_E2_MASK),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)),
++      PINCTRL_CONF_DESC(40, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
++};
++
++static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = {
++      PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK),
++      PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK),
++      PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK),
++      PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK),
++      PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK),
++      PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK),
++      PINCTRL_CONF_DESC(8, REG_I2C_SDA_E4, UART1_TXD_E4_MASK),
++      PINCTRL_CONF_DESC(9, REG_I2C_SDA_E4, UART1_RXD_E4_MASK),
++      PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)),
++      PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)),
++      PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)),
++      PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)),
++      PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)),
++      PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)),
++      PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)),
++      PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)),
++      PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)),
++      PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)),
++      PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)),
++      PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)),
++      PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)),
++      PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)),
++      PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)),
++      PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)),
++      PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)),
++      PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)),
++      PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)),
++      PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)),
++      PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)),
++      PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)),
++      PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)),
++      PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)),
++      PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)),
++      PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)),
++      PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)),
++      PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)),
++      PINCTRL_CONF_DESC(40, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
++      PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
++};
++
++static const struct airoha_pinctrl_match_data pinctrl_match_data = {
++      .pinctrl_name = KBUILD_MODNAME,
++      .pinctrl_owner = THIS_MODULE,
++      .pins = pinctrl_pins,
++      .num_pins = ARRAY_SIZE(pinctrl_pins),
++      .grps = pinctrl_groups,
++      .num_grps = ARRAY_SIZE(pinctrl_groups),
++      .funcs = pinctrl_funcs,
++      .num_funcs = ARRAY_SIZE(pinctrl_funcs),
++      .confs_info = {
++              [AIROHA_PINCTRL_CONFS_PULLUP] = {
++                      .confs = pinctrl_pullup_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pullup_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_PULLDOWN] = {
++                      .confs = pinctrl_pulldown_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E2] = {
++                      .confs = pinctrl_drive_e2_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf),
++              },
++              [AIROHA_PINCTRL_CONFS_DRIVE_E4] = {
++                      .confs = pinctrl_drive_e4_conf,
++                      .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf),
++              },
++      },
++};
++
++static const struct of_device_id airoha_pinctrl_of_match[] = {
++      { .compatible = "airoha,en7523-pinctrl", .data = &pinctrl_match_data },
++      { /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match);
++
++static struct platform_driver airoha_pinctrl_driver = {
++      .probe = airoha_pinctrl_probe,
++      .driver = {
++              .name = "pinctrl-airoha-en7523",
++              .of_match_table = airoha_pinctrl_of_match,
++      },
++};
++module_platform_driver(airoha_pinctrl_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>");
++MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>");
++MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>");
++MODULE_AUTHOR("Matheus Sampaio Queiroga <srherobrine20@gmail.com>");
++MODULE_AUTHOR("Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>");
++MODULE_DESCRIPTION("Pinctrl driver for Airoha EN7523 SoC");

diff --git a/target/linux/airoha/patches-6.18/202-28-v7.3-pinctrl-airoha-try-to-find-chip-scu-node-by-phan.patch b/target/linux/airoha/patches-6.18/202-28-v7.3-pinctrl-airoha-try-to-find-chip-scu-node-by-phan.patch
new file mode 100644 (file)
index 0000000..951f2bd
--- /dev/null
+++ b/target/linux/airoha/patches-6.18/202-28-v7.3-pinctrl-airoha-try-to-find-chip-scu-node-by-phan.patch
@@ -0,0 +1,77 @@
+From 05663c83428fc5550f6d320f1bbddcaed72961ad Mon Sep 17 00:00:00 2001
+From: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+Date: Tue, 16 Jun 2026 08:56:36 +0300
+Subject: [PATCH v11 35/37] pinctrl: airoha: try to find chip scu node by
+ phandle first
+
+The "airoha,en7581-chip-scu" is not a good compatible string in the en7523
+case. Let's search chip scu regmap with "airoha,chip-scu" phangle first
+and fallback to SoC specific chip scu compatible string on failure.
+
+Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
+---
+ drivers/pinctrl/airoha/airoha-common.h  | 1 +
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 9 ++++++---
+ drivers/pinctrl/airoha/pinctrl-an7581.c | 1 +
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 1 +
+ drivers/pinctrl/airoha/pinctrl-en7523.c | 1 +
+ 5 files changed, 10 insertions(+), 3 deletions(-)
+
+--- a/drivers/pinctrl/airoha/airoha-common.h
++++ b/drivers/pinctrl/airoha/airoha-common.h
+@@ -130,6 +130,7 @@ struct airoha_pinctrl {
+ };
+ 
+ struct airoha_pinctrl_match_data {
++      const char *chip_scu_compatible;
+       const char *pinctrl_name;
+       struct module *pinctrl_owner;
+       const struct pinctrl_pin_desc *pins;
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -792,9 +792,12 @@ int airoha_pinctrl_probe(struct platform
+       if (IS_ERR(pinctrl->regmap))
+               return PTR_ERR(pinctrl->regmap);
+ 
+-      map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");
+-      if (IS_ERR(map))
+-              return PTR_ERR(map);
++      map = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "airoha,chip-scu");
++      if (IS_ERR_OR_NULL(map)) {
++              map = syscon_regmap_lookup_by_compatible(data->chip_scu_compatible);
++              if (IS_ERR(map))
++                      return PTR_ERR(map);
++      }
+ 
+       pinctrl->chip_scu = map;
+ 
+--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
+@@ -1432,6 +1432,7 @@ static const struct airoha_pinctrl_conf
+ };
+ 
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
++      .chip_scu_compatible = "airoha,en7581-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+       .pinctrl_owner = THIS_MODULE,
+       .pins = pinctrl_pins,
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -1462,6 +1462,7 @@ static const struct airoha_pinctrl_conf
+ };
+ 
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
++      .chip_scu_compatible = "airoha,en7581-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+       .pinctrl_owner = THIS_MODULE,
+       .pins = pinctrl_pins,
+--- a/drivers/pinctrl/airoha/pinctrl-en7523.c
++++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
+@@ -1104,6 +1104,7 @@ static const struct airoha_pinctrl_conf
+ };
+ 
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
++      .chip_scu_compatible = "airoha,en7523-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+       .pinctrl_owner = THIS_MODULE,
+       .pins = pinctrl_pins,

diff --git a/target/linux/airoha/patches-6.18/203-01-pinctrl-airoha-fix-setting-of-GPIO-direction.patch b/target/linux/airoha/patches-6.18/203-01-pinctrl-airoha-fix-setting-of-GPIO-direction.patch
index 8c3c231da40cfb45a6777cb653e630ade6dc14f6..b902756a5fee02279f40b9ef07515fdfa8e5637b 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-01-pinctrl-airoha-fix-setting-of-GPIO-direction.patch
+++ b/target/linux/airoha/patches-6.18/203-01-pinctrl-airoha-fix-setting-of-GPIO-direction.patch
@@ -1,7 +1,7 @@
-From 69b8875f6290a1518131e4a1c7fb8b73bc8ea6be Mon Sep 17 00:00:00 2001
+From 2b99a9d8e8d955cb8a27a36e703b5421b624289f Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Thu, 12 Mar 2026 19:13:39 +0100
-Subject: [PATCH] pinctrl: airoha: fix setting of GPIO direction
+Subject: [PATCH 1/4] pinctrl: airoha: fix setting of GPIO direction
 
 The GPIO_CTRL registers have two bits per GPIO where the values 0x2 and 0x3
 are reserved. It can happen that both bits in GPIO_CTRL of a GPIO are set when
@@ -20,27 +20,28 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 
 --- a/drivers/pinctrl/airoha/pinctrl-airoha.c
 +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -2627,7 +2627,7 @@ static int airoha_pinmux_set_direction(s
+@@ -164,7 +164,7 @@ static int airoha_gpio_set_direction(str
  {
-       struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+       struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip);
        u32 mask, index;
--      int err, pin;
-+      int err, pin, offset;
+-      int err;
++      int err, offset;
  
-       pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p);
-       if (pin < 0)
-@@ -2642,11 +2642,12 @@ static int airoha_pinmux_set_direction(s
+       /* set output enable */
+       mask = BIT(gpio % AIROHA_PIN_BANK_SIZE);
+@@ -176,12 +176,13 @@ static int airoha_gpio_set_direction(str
                return err;
  
        /* set direction */
--      mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN));
-+      offset = 2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN);
+-      mask = BIT(2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN));
++      offset = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN);
 +      mask = GENMASK(offset + 1, offset); /* always clear the two bits per GPIO */
-       index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN;
+       index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN;
+ 
        return regmap_update_bits(pinctrl->regmap,
-                                 pinctrl->gpiochip.dir[index], mask,
+                                 pinctrl->gpio_regs->dir[index], mask,
 -                                !input ? mask : 0);
 +                                !input ? BIT(offset) : 0);
  }
  
- static const struct pinmux_ops airoha_pmxops = {
+ static int airoha_gpio_direction_input(struct gpio_chip *chip,

diff --git a/target/linux/airoha/patches-6.18/203-02-pinctrl-airoha-reset-SCU-IOMUX-registers-at-probe.patch b/target/linux/airoha/patches-6.18/203-02-pinctrl-airoha-reset-SCU-IOMUX-registers-at-probe.patch
index 9384683e02ec15741ae458648be96660646b20b5..79722643b036b87bf1c1cdb2ce448be72c3b7835 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-02-pinctrl-airoha-reset-SCU-IOMUX-registers-at-probe.patch
+++ b/target/linux/airoha/patches-6.18/203-02-pinctrl-airoha-reset-SCU-IOMUX-registers-at-probe.patch
@@ -1,7 +1,7 @@
-From e39b75a93f37d7ea948ddc02749229742b2aa3a0 Mon Sep 17 00:00:00 2001
+From 7f3f8725907245175ea6ab3b2caccc326dfa4926 Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Fri, 3 Jul 2026 21:36:00 +0200
-Subject: [PATCH] pinctrl: airoha: reset SCU IOMUX registers at probe
+Subject: [PATCH 2/4] pinctrl: airoha: reset SCU IOMUX registers at probe
 
 Add a per-variant table of SCU registers to reset at probe time, so
 bootloader modifications to IOMUX configuration don't silently shadow
@@ -13,33 +13,21 @@ simply write 0 to each. On AN7583 the high bits 15-26 of REG_GPIO_PON_MODE
 GPIO_MODE_MASK for those bits, leaving bits 23-24 at 0 so the kernel
 console UART stays active without a pinctrl-0 declaration.
 
+Also extend patch on EN7523 SoC case
+
 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 ---
- drivers/pinctrl/airoha/pinctrl-airoha.c | 46 +++++++++++++++++++++++++
- 1 file changed, 46 insertions(+)
+ drivers/pinctrl/airoha/airoha-common.h  |  7 +++++++
+ drivers/pinctrl/airoha/pinctrl-airoha.c | 13 +++++++++++++
+ drivers/pinctrl/airoha/pinctrl-an7581.c | 10 ++++++++++
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 14 ++++++++++++++
+ drivers/pinctrl/airoha/pinctrl-en7523.c | 10 ++++++++++
+ 5 files changed, 54 insertions(+)
 
---- a/drivers/pinctrl/airoha/pinctrl-airoha.c
-+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -84,6 +84,7 @@
- #define GPIO_SPI_CS1_MODE_MASK                        BIT(0)
- 
- #define REG_GPIO_PON_MODE                     0x021c
-+#define AN7583_GPIO_MODE_MASK                 (GENMASK(22, 15) | GENMASK(26, 25))
- #define GPIO_PARALLEL_NAND_MODE_MASK          BIT(14)
- #define GPIO_SGMII_MDIO_MODE_MASK             BIT(13)
- #define GPIO_PCIE_RESET2_MASK                 BIT(12)
-@@ -107,6 +108,9 @@
- #define REG_FORCE_GPIO_EN                     0x0228
- #define FORCE_GPIO_EN(n)                      BIT(n)
- 
-+/* AN7583-only */
-+#define REG_FORCE_GPIO32_EN                   0x022C
-+
- /* LED MAP */
- #define REG_LAN_LED0_MAPPING                  0x027c
- #define REG_LAN_LED1_MAPPING                  0x0280
-@@ -403,6 +407,11 @@ struct airoha_pinctrl {
-       struct airoha_pinctrl_gpiochip gpiochip;
+--- a/drivers/pinctrl/airoha/airoha-common.h
++++ b/drivers/pinctrl/airoha/airoha-common.h
+@@ -129,6 +129,11 @@ struct airoha_pinctrl {
+       struct airoha_gpiochip_regs *gpio_regs;
  };
  
 +struct airoha_pinctrl_hwinit_regs {
@@ -48,9 +36,9 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 +};
 +
  struct airoha_pinctrl_match_data {
-       const struct pinctrl_pin_desc *pins;
-       const unsigned int num_pins;
-@@ -411,6 +420,8 @@ struct airoha_pinctrl_match_data {
+       const char *chip_scu_compatible;
+       const char *pinctrl_name;
+@@ -140,6 +145,8 @@ struct airoha_pinctrl_match_data {
        const struct airoha_pinctrl_func *funcs;
        const unsigned int num_funcs;
        const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX];
@@ -58,38 +46,15 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 +      const unsigned int num_hwinit_regs;
  };
  
- static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
-@@ -2981,6 +2992,23 @@ static const struct pinctrl_ops airoha_p
-       .dt_free_map = pinconf_generic_dt_free_map,
- };
- 
-+static const struct airoha_pinctrl_hwinit_regs en7581_hwinit_regs[] = {
-+      { REG_GPIO_2ND_I2C_MODE, 0 },
-+      { REG_GPIO_SPI_CS1_MODE, 0 },
-+      { REG_GPIO_PON_MODE, 0 },
-+      { REG_NPU_UART_EN, 0 },
-+      { REG_FORCE_GPIO_EN, 0 },
-+};
-+
-+static const struct airoha_pinctrl_hwinit_regs an7583_hwinit_regs[] = {
-+      { REG_GPIO_2ND_I2C_MODE, 0 },
-+      { REG_GPIO_SPI_CS1_MODE, 0 },
-+      { REG_GPIO_PON_MODE, AN7583_GPIO_MODE_MASK },
-+      { REG_NPU_UART_EN, 0 },
-+      { REG_FORCE_GPIO_EN, 0 },
-+      { REG_FORCE_GPIO32_EN, 0 },
-+};
-+
- static int airoha_pinctrl_probe(struct platform_device *pdev)
- {
-       const struct airoha_pinctrl_match_data *data;
-@@ -3005,6 +3033,20 @@ static int airoha_pinctrl_probe(struct p
+ int airoha_pinctrl_probe(struct platform_device *pdev);
+--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
++++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
+@@ -802,6 +802,19 @@ int airoha_pinctrl_probe(struct platform
  
        pinctrl->chip_scu = map;
  
 +      /*
 +       * Reset all SCU mux register to reset defaults to undo bootloader modifications.
-+       * For AN7583 set default mux config to GPIO to get same behavior as on AN7581.
 +       */
 +      for (i = 0; i < data->num_hwinit_regs; i++) {
 +              err = regmap_write(pinctrl->chip_scu,
@@ -102,23 +67,101 @@ Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 +      }
 +
        /* Init pinctrl desc struct */
-       pinctrl->desc.name = KBUILD_MODNAME;
-       pinctrl->desc.owner = THIS_MODULE;
-@@ -3067,6 +3109,8 @@ static const struct airoha_pinctrl_match
-       .num_grps = ARRAY_SIZE(en7581_pinctrl_groups),
-       .funcs = en7581_pinctrl_funcs,
-       .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs),
-+      .hwinit_regs = en7581_hwinit_regs,
-+      .num_hwinit_regs = ARRAY_SIZE(en7581_hwinit_regs),
+       pinctrl->desc.name = data->pinctrl_name;
+       pinctrl->desc.owner = data->pinctrl_owner;
+--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
+@@ -1431,6 +1431,14 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
+ };
+ 
++static const struct airoha_pinctrl_hwinit_regs hwinit_regs[] = {
++      { REG_GPIO_2ND_I2C_MODE, 0 },
++      { REG_GPIO_SPI_CS1_MODE, 0 },
++      { REG_GPIO_PON_MODE, 0 },
++      { REG_NPU_UART_EN, 0 },
++      { REG_FORCE_GPIO_EN, 0 },
++};
++
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+       .chip_scu_compatible = "airoha,en7581-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+@@ -1441,6 +1449,8 @@ static const struct airoha_pinctrl_match
+       .num_grps = ARRAY_SIZE(pinctrl_groups),
+       .funcs = pinctrl_funcs,
+       .num_funcs = ARRAY_SIZE(pinctrl_funcs),
++      .hwinit_regs = hwinit_regs,
++      .num_hwinit_regs = ARRAY_SIZE(hwinit_regs),
+       .confs_info = {
+               [AIROHA_PINCTRL_CONFS_PULLUP] = {
+                       .confs = pinctrl_pullup_conf,
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -39,6 +39,7 @@
+ 
+ #define REG_GPIO_PON_MODE                     0x021c
+ #define GPIO_PON_ALT_MODE_MASK                        BIT(27)
++#define GPIO_MODE_MASK                                (GENMASK(22, 15) | GENMASK(26, 25))
+ #define MDIO_0_GPIO_MODE_MASK                 BIT(26)
+ #define MDC_0_GPIO_MODE_MASK                  BIT(25)
+ #define UART_RXD_GPIO_MODE_MASK                       BIT(24)
+@@ -75,6 +76,8 @@
+ #define REG_FORCE_GPIO_EN                     0x0228
+ #define FORCE_GPIO_EN(n)                      BIT(n)
+ 
++#define REG_FORCE_GPIO32_EN                   0x022C
++
+ /* LED MAP */
+ #define REG_LAN_LED0_MAPPING                  0x027c
+ #define REG_LAN_LED1_MAPPING                  0x0280
+@@ -1461,6 +1464,15 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
+ };
+ 
++static const struct airoha_pinctrl_hwinit_regs hwinit_regs[] = {
++      { REG_SW_TOD_1PPS_MODE, 0 },
++      { REG_GPIO_SPI_CS1_MODE, 0 },
++      { REG_GPIO_PON_MODE, GPIO_MODE_MASK },
++      { REG_NPU_UART_EN, 0 },
++      { REG_FORCE_GPIO_EN, 0 },
++      { REG_FORCE_GPIO32_EN, 0 },
++};
++
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+       .chip_scu_compatible = "airoha,en7581-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+@@ -1471,6 +1483,8 @@ static const struct airoha_pinctrl_match
+       .num_grps = ARRAY_SIZE(pinctrl_groups),
+       .funcs = pinctrl_funcs,
+       .num_funcs = ARRAY_SIZE(pinctrl_funcs),
++      .hwinit_regs = hwinit_regs,
++      .num_hwinit_regs = ARRAY_SIZE(hwinit_regs),
        .confs_info = {
                [AIROHA_PINCTRL_CONFS_PULLUP] = {
-                       .confs = en7581_pinctrl_pullup_conf,
-@@ -3098,6 +3142,8 @@ static const struct airoha_pinctrl_match
-       .num_grps = ARRAY_SIZE(an7583_pinctrl_groups),
-       .funcs = an7583_pinctrl_funcs,
-       .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs),
-+      .hwinit_regs = an7583_hwinit_regs,
-+      .num_hwinit_regs = ARRAY_SIZE(an7583_hwinit_regs),
+                       .confs = pinctrl_pullup_conf,
+--- a/drivers/pinctrl/airoha/pinctrl-en7523.c
++++ b/drivers/pinctrl/airoha/pinctrl-en7523.c
+@@ -1103,6 +1103,14 @@ static const struct airoha_pinctrl_conf
+       PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
+ };
+ 
++static const struct airoha_pinctrl_hwinit_regs hwinit_regs[] = {
++      { REG_GPIO_2ND_I2C_MODE, 0 },
++      { REG_GPIO_SPI_CS1_MODE, 0 },
++      { REG_GPIO_PON_MODE, 0 },
++      { REG_NPU_UART_EN, 0 },
++      { REG_FORCE_GPIO_EN, 0 },
++};
++
+ static const struct airoha_pinctrl_match_data pinctrl_match_data = {
+       .chip_scu_compatible = "airoha,en7523-chip-scu",
+       .pinctrl_name = KBUILD_MODNAME,
+@@ -1113,6 +1121,8 @@ static const struct airoha_pinctrl_match
+       .num_grps = ARRAY_SIZE(pinctrl_groups),
+       .funcs = pinctrl_funcs,
+       .num_funcs = ARRAY_SIZE(pinctrl_funcs),
++      .hwinit_regs = hwinit_regs,
++      .num_hwinit_regs = ARRAY_SIZE(hwinit_regs),
        .confs_info = {
                [AIROHA_PINCTRL_CONFS_PULLUP] = {
-                       .confs = an7583_pinctrl_pullup_conf,
+                       .confs = pinctrl_pullup_conf,

diff --git a/target/linux/airoha/patches-6.18/203-06-pinctrl-airoha-fix-AN7583-SPI-pin-mux-config.patch b/target/linux/airoha/patches-6.18/203-06-pinctrl-airoha-fix-AN7583-SPI-pin-mux-config.patch
index 9dfe867c74ed26c87e68059721b3ffe0adca2de0..a92b4fabd2f6e1180a5ce496148d8193c27f5072 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-06-pinctrl-airoha-fix-AN7583-SPI-pin-mux-config.patch
+++ b/target/linux/airoha/patches-6.18/203-06-pinctrl-airoha-fix-AN7583-SPI-pin-mux-config.patch
@@ -1,10 +1,8 @@
-From c4ecab08e53151f7bc39ca4604124acf85cd7595 Mon Sep 17 00:00:00 2001
+From 23e278f5102bf1d31b3ea0e66da96a014bbfa5bb Mon Sep 17 00:00:00 2001
 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 Date: Sat, 4 Jul 2026 00:52:18 +0200
-Subject: [PATCH] pinctrl: airoha: fix AN7583 SPI pin mux config
+Subject: [PATCH 3/4] pinctrl: airoha: an7583: fix SPI pin mux config
 
-The AN7583 "spi" group pointed at pins 28-31 (2nd SPI extension bus)
-instead of pins 45-48 (1st SPI boot-flash bus). Additionally the
 "spi" func_group entry was missing, so any board DTS referencing
 function = "spi"; groups = "spi" would fail with -EINVAL.
 
@@ -14,88 +12,45 @@ in GPIO mode by default), so the func_group entry must clear those
 bits to enable the SPI function. EN7581 SPI pins are dedicated-
 function pads with no GPIO alternative and need no register write.
 
-Fix this by correcting an7583_spi_pins[], adding
-AN7583_SPI_GPIO_MODE_MASK (GENMASK(22,19)), and splitting
-spi_func_group[] into shared (EN7581) and AN7583-specific variants.
-The new an7583_spi_func_group[] adds the "spi" entry that clears
-bits 19-22 of REG_GPIO_PON_MODE.
+Fix this by adding mux for "spi" group
 
 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
 ---
- drivers/pinctrl/airoha/pinctrl-airoha.c | 37 +++++++++++++++++++++++--
- 1 file changed, 35 insertions(+), 2 deletions(-)
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
 
---- a/drivers/pinctrl/airoha/pinctrl-airoha.c
-+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -87,6 +87,7 @@
- #define AN7583_GPIO_MODE_MASK                 (GENMASK(22, 15) | GENMASK(26, 25))
- #define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
- #define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
-+#define AN7583_SPI_GPIO_MODE_MASK             GENMASK(22, 19)
- #define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
- #define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
- #define AN7583_I2C0_SDA_GPIO_MODE_MASK                BIT(16)
-@@ -736,7 +737,7 @@ static const int an7583_jtag_udi_pins[]
- static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 };
- static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 };
- static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 };
--static const int an7583_spi_pins[] = { 28, 29, 30, 31 };
-+static const int an7583_spi_pins[] = { 45, 46, 47, 48 };
- static const int an7583_spi_quad_pins[] = { 25, 26 };
- static const int an7583_spi_cs1_pins[] = { 27 };
- static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 };
-@@ -890,6 +891,7 @@ static const char *const an7583_i2c_grou
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -44,6 +44,7 @@
+ #define MDC_0_GPIO_MODE_MASK                  BIT(25)
+ #define UART_RXD_GPIO_MODE_MASK                       BIT(24)
+ #define UART_TXD_GPIO_MODE_MASK                       BIT(23)
++#define SPI_GPIO_MODE_MASK                    GENMASK(22, 19)
+ #define SPI_MISO_GPIO_MODE_MASK                       BIT(22)
+ #define SPI_MOSI_GPIO_MODE_MASK                       BIT(21)
+ #define SPI_CS_GPIO_MODE_MASK                 BIT(20)
+@@ -587,7 +588,7 @@ static const char *const uart_groups[] =
+ static const char *const i2c_groups[] = { "i2c0", "i2c1" };
  static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" };
  static const char *const pcm_groups[] = { "pcm1", "pcm2" };
- static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
-+static const char *const an7583_spi_groups[] = { "spi", "spi_quad", "spi_cs1" };
- static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int",
-                                             "pcm_spi_rst", "pcm_spi_cs1",
-                                             "pcm_spi_cs2_p156",
-@@ -1265,6 +1267,37 @@ static const struct airoha_pinctrl_func_
-       },
+-static const char *const spi_groups[] = { "spi_quad", "spi_cs1" };
++static const char *const spi_groups[] = { "spi", "spi_quad", "spi_cs1" };
+ static const char *const pcm_spi_groups[] = {
+       "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1"
  };
+@@ -864,6 +865,15 @@ static const struct airoha_pinctrl_func_
  
-+static const struct airoha_pinctrl_func_group an7583_spi_func_group[] = {
-+      {
+ static const struct airoha_pinctrl_func_group spi_func_group[] = {
+       {
 +              .name = "spi",
 +              .regmap[0] = {
 +                      AIROHA_FUNC_MUX,
 +                      REG_GPIO_PON_MODE,
-+                      AN7583_SPI_GPIO_MODE_MASK,
++                      SPI_GPIO_MODE_MASK,
 +                      0
 +              },
 +              .regmap_size = 1,
 +      }, {
-+              .name = "spi_quad",
-+              .regmap[0] = {
-+                      AIROHA_FUNC_MUX,
-+                      REG_GPIO_SPI_CS1_MODE,
-+                      GPIO_SPI_QUAD_MODE_MASK,
-+                      GPIO_SPI_QUAD_MODE_MASK
-+              },
-+              .regmap_size = 1,
-+      }, {
-+              .name = "spi_cs1",
-+              .regmap[0] = {
-+                      AIROHA_FUNC_MUX,
-+                      REG_GPIO_SPI_CS1_MODE,
-+                      GPIO_SPI_CS1_MODE_MASK,
-+                      GPIO_SPI_CS1_MODE_MASK
-+              },
-+              .regmap_size = 1,
-+      },
-+};
-+
- static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = {
-       {
-               .name = "pcm_spi",
-@@ -1898,7 +1931,7 @@ static const struct airoha_pinctrl_func
-       PINCTRL_FUNC_DESC("i2c", an7583_i2c),
-       PINCTRL_FUNC_DESC("jtag", jtag),
-       PINCTRL_FUNC_DESC("pcm", pcm),
--      PINCTRL_FUNC_DESC("spi", spi),
-+      PINCTRL_FUNC_DESC("spi", an7583_spi),
-       PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
-       PINCTRL_FUNC_DESC("emmc", emmc),
-       PINCTRL_FUNC_DESC("pnand", pnand),
+               .name = "spi_quad",
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,

diff --git a/target/linux/airoha/patches-6.18/203-07-pinctrl-airoha-remove-nonexistent-AN7583-PCM-SPI-groups.patch b/target/linux/airoha/patches-6.18/203-07-pinctrl-airoha-remove-nonexistent-AN7583-PCM-SPI-groups.patch
deleted file mode 100644 (file)
index 28c4133..0000000
--- a/target/linux/airoha/patches-6.18/203-07-pinctrl-airoha-remove-nonexistent-AN7583-PCM-SPI-groups.patch
+++ /dev/null
@@ -1,72 +0,0 @@
-From 90b810be65087288a2262ec6428ad64a8bdcf77c Mon Sep 17 00:00:00 2001
-From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
-Date: Sat, 4 Jul 2026 01:23:28 +0200
-Subject: [PATCH] pinctrl: airoha: remove nonexistent AN7583 PCM SPI groups
-
-The an7583_pcm_spi_groups[] references "pcm_spi_int", "pcm_spi_cs2",
-"pcm_spi_cs3" and "pcm_spi_cs4". None of these groups are defined in
-an7583_pinctrl_groups[], they exist only on AN7581. The PCM SPI interface
-on AN7583 only supports CLK, CS0, CS1, MOSI, MISO and RESET. Any board
-DTS referencing these groups would silently get -EINVAL from
-airoha_pinmux_set_mux().
-
-Remove the nonexistent group names from an7583_pcm_spi_groups[] and
-their matching regmap entries from an7583_pcm_spi_func_group[].
-
-Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
----
- drivers/pinctrl/airoha/pinctrl-airoha.c | 36 -------------------------
- 1 file changed, 36 deletions(-)
-
---- a/drivers/pinctrl/airoha/pinctrl-airoha.c
-+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -1385,15 +1385,6 @@ static const struct airoha_pinctrl_func_
-               },
-               .regmap_size = 1,
-       }, {
--              .name = "pcm_spi_int",
--              .regmap[0] = {
--                      AIROHA_FUNC_MUX,
--                      REG_GPIO_SPI_CS1_MODE,
--                      GPIO_PCM_INT_MODE_MASK,
--                      GPIO_PCM_INT_MODE_MASK
--              },
--              .regmap_size = 1,
--      }, {
-               .name = "pcm_spi_rst",
-               .regmap[0] = {
-                       AIROHA_FUNC_MUX,
-@@ -1411,33 +1402,6 @@ static const struct airoha_pinctrl_func_
-                       GPIO_PCM_SPI_CS1_MODE_MASK
-               },
-               .regmap_size = 1,
--      }, {
--              .name = "pcm_spi_cs2",
--              .regmap[0] = {
--                      AIROHA_FUNC_MUX,
--                      REG_GPIO_SPI_CS1_MODE,
--                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK,
--                      AN7583_GPIO_PCM_SPI_CS2_MODE_MASK
--              },
--              .regmap_size = 1,
--      }, {
--              .name = "pcm_spi_cs3",
--              .regmap[0] = {
--                      AIROHA_FUNC_MUX,
--                      REG_GPIO_SPI_CS1_MODE,
--                      GPIO_PCM_SPI_CS3_MODE_MASK,
--                      GPIO_PCM_SPI_CS3_MODE_MASK
--              },
--              .regmap_size = 1,
--      }, {
--              .name = "pcm_spi_cs4",
--              .regmap[0] = {
--                      AIROHA_FUNC_MUX,
--                      REG_GPIO_SPI_CS1_MODE,
--                      GPIO_PCM_SPI_CS4_MODE_MASK,
--                      GPIO_PCM_SPI_CS4_MODE_MASK
--              },
--              .regmap_size = 1,
-       },
- };
- 

diff --git a/target/linux/airoha/patches-6.18/203-08-pinctrl-airoha-fix-AN7583-eMMC-pin-mux-config.patch b/target/linux/airoha/patches-6.18/203-08-pinctrl-airoha-fix-AN7583-eMMC-pin-mux-config.patch
index b95ffd65bbe351af04916b9f919bd845ba33a1e7..91271d8522bc0014f06c5bd0fa482a155083ba6a 100644 (file)
--- a/target/linux/airoha/patches-6.18/203-08-pinctrl-airoha-fix-AN7583-eMMC-pin-mux-config.patch
+++ b/target/linux/airoha/patches-6.18/203-08-pinctrl-airoha-fix-AN7583-eMMC-pin-mux-config.patch
@@ -1,64 +1,36 @@
+From 624a2ba252a64a87d2fc01ded1d5151d4d652731 Mon Sep 17 00:00:00 2001
 From: Robert Marko <robert.marko@sartura.hr>
 Date: Fri, 7 Aug 2026 14:30:00 +0200
-Subject: [PATCH] pinctrl: airoha: fix AN7583 eMMC pin mux config
+Subject: [PATCH 4/4] pinctrl: airoha: an7583: fix eMMC pin mux config
 
 The AN7583 eMMC group uses pins 45-47, which are shared with the first
 SPI bus and GPIO. After the SCU IOMUX registers are reset at probe, the
 GPIO overrides for these pins remain enabled because the shared eMMC
 function group only sets GPIO_EMMC_MODE_MASK.
 
-Add a dedicated AN7583 eMMC function group which also clears the GPIO
-mode bits for pins 45-47 when selecting eMMC.
+Fix this by clearing the GPIO mode bits for pins 45-47 when selecting eMMC.
 
 Signed-off-by: Robert Marko <robert.marko@sartura.hr>
 ---
- drivers/pinctrl/airoha/pinctrl-airoha.c | 17 ++++++++++++++++-
- 1 file changed, 16 insertions(+), 1 deletion(-)
+ drivers/pinctrl/airoha/pinctrl-an7583.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
 
---- a/drivers/pinctrl/airoha/pinctrl-airoha.c
-+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -87,6 +87,7 @@
- #define AN7583_GPIO_MODE_MASK                 (GENMASK(22, 15) | GENMASK(26, 25))
- #define AN7583_MDC_0_GPIO_MODE_MASK           BIT(25)
- #define AN7583_MDIO_0_GPIO_MODE_MASK          BIT(26)
-+#define AN7583_EMMC_GPIO_MODE_MASK            GENMASK(21, 19)
- #define AN7583_SPI_GPIO_MODE_MASK             GENMASK(22, 19)
- #define AN7583_I2C1_SDA_GPIO_MODE_MASK                BIT(18)
- #define AN7583_I2C1_SCL_GPIO_MODE_MASK                BIT(17)
-@@ -901,6 +902,7 @@ static const char *const an7583_pcm_spi_
-                                                    "pcm_spi_rst", "pcm_spi_cs1" };
- static const char *const i2s_groups[] = { "i2s" };
- static const char *const emmc_groups[] = { "emmc" };
-+static const char *const an7583_emmc_groups[] = { "emmc" };
- static const char *const pnand_groups[] = { "pnand" };
- static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
-                                                "pcie_reset2" };
-@@ -1431,6 +1433,19 @@ static const struct airoha_pinctrl_func_
-       },
- };
- 
-+static const struct airoha_pinctrl_func_group an7583_emmc_func_group[] = {
-+      {
-+              .name = "emmc",
-+              .regmap[0] = {
-+                      AIROHA_FUNC_MUX,
-+                      REG_GPIO_PON_MODE,
-+                      GPIO_EMMC_MODE_MASK | AN7583_EMMC_GPIO_MODE_MASK,
-+                      GPIO_EMMC_MODE_MASK
-+              },
-+              .regmap_size = 1,
-+      },
-+};
-+
- static const struct airoha_pinctrl_func_group pnand_func_group[] = {
-       {
-               .name = "pnand",
-@@ -1897,7 +1912,7 @@ static const struct airoha_pinctrl_func
-       PINCTRL_FUNC_DESC("pcm", pcm),
-       PINCTRL_FUNC_DESC("spi", an7583_spi),
-       PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi),
--      PINCTRL_FUNC_DESC("emmc", emmc),
-+      PINCTRL_FUNC_DESC("emmc", an7583_emmc),
-       PINCTRL_FUNC_DESC("pnand", pnand),
-       PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset),
-       PINCTRL_FUNC_DESC("pwm", an7583_pwm),
+--- a/drivers/pinctrl/airoha/pinctrl-an7583.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7583.c
+@@ -45,6 +45,7 @@
+ #define UART_RXD_GPIO_MODE_MASK                       BIT(24)
+ #define UART_TXD_GPIO_MODE_MASK                       BIT(23)
+ #define SPI_GPIO_MODE_MASK                    GENMASK(22, 19)
++#define EMMC_GPIO_MODE_MASK                   GENMASK(21, 19)
+ #define SPI_MISO_GPIO_MODE_MASK                       BIT(22)
+ #define SPI_MOSI_GPIO_MODE_MASK                       BIT(21)
+ #define SPI_CS_GPIO_MODE_MASK                 BIT(20)
+@@ -994,7 +995,7 @@ static const struct airoha_pinctrl_func_
+               .regmap[0] = {
+                       AIROHA_FUNC_MUX,
+                       REG_GPIO_PON_MODE,
+-                      GPIO_EMMC_MODE_MASK,
++                      GPIO_EMMC_MODE_MASK | EMMC_GPIO_MODE_MASK,
+                       GPIO_EMMC_MODE_MASK
+               },
+               .regmap_size = 1,

diff --git a/target/linux/airoha/patches-6.18/202-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch b/target/linux/airoha/patches-6.18/203-09-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch
similarity index 67%
rename from target/linux/airoha/patches-6.18/202-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch
rename to target/linux/airoha/patches-6.18/203-09-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch
index 151605c6e4ae4d1a0865fe2feff233dc27a3b839..9b049bad992cde9b18d90722c698e3a668ad4f82 100644 (file)
--- a/target/linux/airoha/patches-6.18/202-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch
+++ b/target/linux/airoha/patches-6.18/203-09-pinctrl-airoha-permit-GPIO43-46-for-PHY-LED0.patch
@@ -1,4 +1,4 @@
-From 6587e2b7993f3e5030eb42083293e2db960ee601 Mon Sep 17 00:00:00 2001
+From 5fae6f9f35dbe0cc94ac663817464276c35267c3 Mon Sep 17 00:00:00 2001
 From: Christian Marangi <ansuelsmth@gmail.com>
 Date: Tue, 10 Mar 2026 16:16:03 +0100
 Subject: [PATCH] pinctrl: airoha: permit GPIO43-46 for PHY LED0
@@ -8,38 +8,37 @@ used for PHY LED0. Add these additional GPIO pins to the function groups.
 
 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 ---
- drivers/pinctrl/airoha/pinctrl-airoha.c | 48 ++++++++++++++++++++++---
- 1 file changed, 44 insertions(+), 4 deletions(-)
+ drivers/pinctrl/airoha/pinctrl-an7581.c | 44 ++++++++++++++++++++++---
+ 1 file changed, 40 insertions(+), 4 deletions(-)
 
---- a/drivers/pinctrl/airoha/pinctrl-airoha.c
-+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
-@@ -931,13 +931,21 @@ static const char *const an7583_pwm_grou
-                                                "gpio46", "gpio47",
-                                                "gpio48" };
- static const char *const phy1_led0_groups[] = { "gpio33", "gpio34",
--                                              "gpio35", "gpio42" };
-+                                              "gpio35", "gpio42",
-+                                              "gpio43", "gpio44",
-+                                              "gpio45", "gpio46" };
- static const char *const phy2_led0_groups[] = { "gpio33", "gpio34",
--                                              "gpio35", "gpio42" };
-+                                              "gpio35", "gpio42",
-+                                              "gpio43", "gpio44",
-+                                              "gpio45", "gpio46" };
- static const char *const phy3_led0_groups[] = { "gpio33", "gpio34",
--                                              "gpio35", "gpio42" };
-+                                              "gpio35", "gpio42",
-+                                              "gpio43", "gpio44",
-+                                              "gpio45", "gpio46" };
- static const char *const phy4_led0_groups[] = { "gpio33", "gpio34",
--                                              "gpio35", "gpio42" };
-+                                              "gpio35", "gpio42",
-+                                              "gpio43", "gpio44",
-+                                              "gpio45", "gpio46" };
- static const char *const phy1_led1_groups[] = { "gpio43", "gpio44",
-                                               "gpio45", "gpio46" };
- static const char *const phy2_led1_groups[] = { "gpio43", "gpio44",
-@@ -1622,6 +1630,14 @@ static const struct airoha_pinctrl_func_
+--- a/drivers/pinctrl/airoha/pinctrl-an7581.c
++++ b/drivers/pinctrl/airoha/pinctrl-an7581.c
+@@ -594,16 +594,20 @@ static const char *const pwm_groups[] =
+       "gpio46", "gpio47", "gpio48", "gpio49"
+ };
+ static const char *const phy1_led0_groups[] = {
+-      "gpio33", "gpio34", "gpio35", "gpio42"
++      "gpio33", "gpio34", "gpio35", "gpio42",
++      "gpio43", "gpio44", "gpio45", "gpio46"
+ };
+ static const char *const phy2_led0_groups[] = {
+-      "gpio33", "gpio34", "gpio35", "gpio42"
++      "gpio33", "gpio34", "gpio35", "gpio42",
++      "gpio43", "gpio44", "gpio45", "gpio46"
+ };
+ static const char *const phy3_led0_groups[] = {
+-      "gpio33", "gpio34", "gpio35", "gpio42"
++      "gpio33", "gpio34", "gpio35", "gpio42",
++      "gpio43", "gpio44", "gpio45", "gpio46"
+ };
+ static const char *const phy4_led0_groups[] = {
+-      "gpio33", "gpio34", "gpio35", "gpio42"
++      "gpio33", "gpio34", "gpio35", "gpio42",
++      "gpio43", "gpio44", "gpio45", "gpio46"
+ };
+ static const char *const phy1_led1_groups[] = {
+       "gpio43", "gpio44", "gpio45", "gpio46"
+@@ -1075,6 +1079,14 @@ static const struct airoha_pinctrl_func_
                                LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)),
        AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
                                LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)),
@@ -54,7 +53,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  };
  
  static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = {
-@@ -1633,6 +1649,14 @@ static const struct airoha_pinctrl_func_
+@@ -1086,6 +1098,14 @@ static const struct airoha_pinctrl_func_
                                LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)),
        AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
                                LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)),
@@ -69,7 +68,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  };
  
  static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = {
-@@ -1644,6 +1668,14 @@ static const struct airoha_pinctrl_func_
+@@ -1097,6 +1117,14 @@ static const struct airoha_pinctrl_func_
                                LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)),
        AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
                                LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)),
@@ -84,7 +83,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  };
  
  static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = {
-@@ -1655,6 +1687,14 @@ static const struct airoha_pinctrl_func_
+@@ -1108,6 +1136,14 @@ static const struct airoha_pinctrl_func_
                                LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)),
        AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK,
                                LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)),