]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
ixgbe: E610: update ACI command structs with EEE fields
authorJedrzej Jagielski <jedrzej.jagielski@intel.com>
Fri, 1 May 2026 06:37:15 +0000 (23:37 -0700)
committerJakub Kicinski <kuba@kernel.org>
Sun, 3 May 2026 02:12:36 +0000 (19:12 -0700)
There were recent changes in some of the ACI commands,
which have been extended with EEE related fields.
Set PHY Config, Get PHY Caps and Get Link Info have been
affected.

Align SW structs to the recent FW changes.

Reviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>
Signed-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>
Tested-by: Rinitha S <sx.rinitha@intel.com>
Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
Link: https://patch.msgid.link/20260430-jk-iwl-net-next-2026-04-30-v1-4-6f27ae1cd073@intel.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
drivers/net/ethernet/intel/ixgbe/ixgbe_e610.c
drivers/net/ethernet/intel/ixgbe/ixgbe_type_e610.h

index 2703207a9efa23f6729f4f43cf49243a32dc011b..a01d991ee2e0906be5be7542927a599acf7139c7 100644 (file)
@@ -1076,6 +1076,7 @@ void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,
        cfg->link_fec_opt = caps->link_fec_options;
        cfg->module_compliance_enforcement =
                caps->module_compliance_enforcement;
+       cfg->eee_entry_delay = caps->eee_entry_delay;
 }
 
 /**
@@ -1404,6 +1405,7 @@ int ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,
        li->topo_media_conflict = link_data.topo_media_conflict;
        li->pacing = link_data.cfg & (IXGBE_ACI_CFG_PACING_M |
                                      IXGBE_ACI_CFG_PACING_TYPE_M);
+       li->eee_status = link_data.eee_status;
 
        /* Update fc info. */
        tx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX);
index cfaaf2fcf7aecdb9e4a227caa461f285d86ea63f..959cacecae49981a8b2c4414c87ad3c706e92d9a 100644 (file)
@@ -323,10 +323,8 @@ struct ixgbe_aci_cmd_get_phy_caps_data {
 #define IXGBE_ACI_PHY_EEE_EN_100BASE_TX                        BIT(0)
 #define IXGBE_ACI_PHY_EEE_EN_1000BASE_T                        BIT(1)
 #define IXGBE_ACI_PHY_EEE_EN_10GBASE_T                 BIT(2)
-#define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX               BIT(3)
-#define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR                        BIT(4)
-#define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR                        BIT(5)
-#define IXGBE_ACI_PHY_EEE_EN_10BASE_T                  BIT(11)
+#define IXGBE_ACI_PHY_EEE_EN_5GBASE_T                  BIT(11)
+#define IXGBE_ACI_PHY_EEE_EN_2_5GBASE_T                        BIT(12)
        __le16 eeer_value;
        u8 phy_id_oui[4]; /* PHY/Module ID connected on the port */
        u8 phy_fw_ver[8];
@@ -356,7 +354,9 @@ struct ixgbe_aci_cmd_get_phy_caps_data {
 #define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS              0xA0
 #define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS             0x86
        u8 qualified_module_count;
-       u8 rsvd2[7];    /* Bytes 47:41 reserved */
+       u8 rsvd2;
+       __le16 eee_entry_delay;
+       u8 rsvd3[4];
 #define IXGBE_ACI_QUAL_MOD_COUNT_MAX                   16
        struct {
                u8 v_oui[3];
@@ -512,8 +512,9 @@ struct ixgbe_aci_cmd_get_link_status_data {
 #define IXGBE_ACI_LINK_SPEED_200GB             BIT(11)
 #define IXGBE_ACI_LINK_SPEED_UNKNOWN           BIT(15)
        __le16 reserved3;
-       u8 ext_fec_status;
-#define IXGBE_ACI_LINK_RS_272_FEC_EN   BIT(0) /* RS 272 FEC enabled */
+       u8 eee_status;
+#define IXGBE_ACI_LINK_EEE_ENABLED             BIT(2)
+#define IXGBE_ACI_LINK_EEE_ACTIVE              BIT(3)
        u8 reserved4;
        __le64 phy_type_low; /* Use values from ICE_PHY_TYPE_LOW_* */
        __le64 phy_type_high; /* Use values from ICE_PHY_TYPE_HIGH_* */
@@ -815,6 +816,7 @@ struct ixgbe_link_status {
         * of ixgbe_aci_get_phy_caps structure
         */
        u8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE];
+       u8 eee_status;
 };
 
 /* Common HW capabilities for SW use */