arm64: dts: renesas: r9a09g057: Add FCPV and VSPD nodes

Add FCPV and VSPD nodes to RZ/V2H(P) SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20251023212314.679303-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 4df32d7e999818c94f8392130b70ee0e36293e89..59dc6025749b9ba662af8c7d09f6614e4b42a329 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -1348,6 +1348,30 @@
                                };
                        };
                };
+
+               fcpvd: fcp@16470000 {
+                       compatible = "renesas,r9a09g057-fcpvd", "renesas,fcpv";
+                       reg = <0 0x16470000 0 0x10000>;
+                       clocks = <&cpg CPG_MOD 0xed>,
+                                <&cpg CPG_MOD 0xee>,
+                                <&cpg CPG_MOD 0xef>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xdc>;
+               };
+
+               vspd: vsp@16480000 {
+                       compatible = "renesas,r9a09g057-vsp2", "renesas,r9a07g044-vsp2";
+                       reg = <0 0x16480000 0 0x10000>;
+                       interrupts = <GIC_SPI 881 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 0xed>,
+                                <&cpg CPG_MOD 0xee>,
+                                <&cpg CPG_MOD 0xef>;
+                       clock-names = "aclk", "pclk", "vclk";
+                       power-domains = <&cpg>;
+                       resets = <&cpg 0xdc>;
+                       renesas,fcp = <&fcpvd>;
+               };
        };
 
        stmmac_axi_setup: stmmac-axi-config {