Allow zero operand in sparc VIS3 cmask patterns.

	* config/sparc/sparc.md (cmask patterns): Allow zero operand.

From-SVN: r180715

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 4848147bf620874bb238b4f3e4b4bb75bb186aa0..ebf8cdc0e588b9b0d1a0754b01417ddb628c7e4c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,5 +1,7 @@
 2011-10-31  David S. Miller  <davem@davemloft.net>
 
+       * config/sparc/sparc.md (cmask patterns): Allow zero operand.
+
        * dwarf2out.c (cached_next_real_insn): New.
        (dwarf2out_end_epilogue): Set it to NULL_RTX.
        (dwarf2out_var_location): Remove cached_next_real_insn local static.

diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 6dd390952c39aa6008694552d634f952c0a92e69..fbd1a8719217bea0c29f54acd170a28331d734c0 100644 (file)
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -8452,7 +8452,7 @@
 ;; Conditional moves are possible via fcmpX --> cmaskX -> bshuffle
 (define_insn "cmask8<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
                    (reg:DI GSR_REG)]
                    UNSPEC_CMASK8))]
   "TARGET_VIS3"
@@ -8460,7 +8460,7 @@
 
 (define_insn "cmask16<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
                    (reg:DI GSR_REG)]
                    UNSPEC_CMASK16))]
   "TARGET_VIS3"
@@ -8468,7 +8468,7 @@
 
 (define_insn "cmask32<P:mode>_vis"
   [(set (reg:DI GSR_REG)
-        (unspec:DI [(match_operand:P 0 "register_operand" "r")
+        (unspec:DI [(match_operand:P 0 "register_or_zero_operand" "rJ")
                    (reg:DI GSR_REG)]
                    UNSPEC_CMASK32))]
   "TARGET_VIS3"