#define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev)))
#define amdgpu_asic_supports_baco(adev) \
((adev)->asic_funcs->supports_baco ? (adev)->asic_funcs->supports_baco((adev)) : 0)
-#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))
+#define amdgpu_asic_pre_asic_init(adev) \
+ { \
+ if ((adev)->asic_funcs && (adev)->asic_funcs->pre_asic_init) \
+ (adev)->asic_funcs->pre_asic_init((adev)); \
+ }
#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \
((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)
#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))
return (nak_r + nak_g);
}
-static void cik_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static const struct amdgpu_asic_funcs cik_asic_funcs =
{
.read_disabled_bios = &cik_read_disabled_bios,
.need_reset_on_init = &cik_need_reset_on_init,
.get_pcie_replay_count = &cik_get_pcie_replay_count,
.supports_baco = &cik_asic_supports_baco,
- .pre_asic_init = &cik_pre_asic_init,
.query_video_codecs = &cik_query_video_codecs,
};
adev->doorbell_index.sdma_doorbell_range = 20;
}
-static void nv_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
bool enter)
{
.need_reset_on_init = &nv_need_reset_on_init,
.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
.supports_baco = &amdgpu_dpm_is_baco_supported,
- .pre_asic_init = &nv_pre_asic_init,
.update_umd_stable_pstate = &nv_update_umd_stable_pstate,
.query_video_codecs = &nv_query_video_codecs,
};
return 0;
}
-static void si_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static const struct amdgpu_asic_funcs si_asic_funcs =
{
.read_disabled_bios = &si_read_disabled_bios,
.need_reset_on_init = &si_need_reset_on_init,
.get_pcie_replay_count = &si_get_pcie_replay_count,
.supports_baco = &si_asic_supports_baco,
- .pre_asic_init = &si_pre_asic_init,
.query_video_codecs = &si_query_video_codecs,
};
.need_reset_on_init = &soc15_need_reset_on_init,
.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
.supports_baco = &soc15_supports_baco,
- .pre_asic_init = &soc15_pre_asic_init,
.query_video_codecs = &soc15_query_video_codecs,
.encode_ext_smn_addressing = &aqua_vanjaram_encode_ext_smn_addressing,
.get_reg_state = &aqua_vanjaram_get_reg_state,
adev->doorbell_index.sdma_doorbell_range = 20;
}
-static void soc21_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
bool enter)
{
.need_reset_on_init = &soc21_need_reset_on_init,
.get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
.supports_baco = &amdgpu_dpm_is_baco_supported,
- .pre_asic_init = &soc21_pre_asic_init,
.query_video_codecs = &soc21_query_video_codecs,
.update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
};
adev->doorbell_index.sdma_doorbell_range = 20;
}
-static void soc24_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static int soc24_update_umd_stable_pstate(struct amdgpu_device *adev,
bool enter)
{
.need_reset_on_init = &soc24_need_reset_on_init,
.get_pcie_replay_count = &soc24_get_pcie_replay_count,
.supports_baco = &amdgpu_dpm_is_baco_supported,
- .pre_asic_init = &soc24_pre_asic_init,
.query_video_codecs = &soc24_query_video_codecs,
.update_umd_stable_pstate = &soc24_update_umd_stable_pstate,
};
return false;
}
-static void vi_pre_asic_init(struct amdgpu_device *adev)
-{
-}
-
static const struct amdgpu_asic_funcs vi_asic_funcs =
{
.read_disabled_bios = &vi_read_disabled_bios,
.need_reset_on_init = &vi_need_reset_on_init,
.get_pcie_replay_count = &vi_get_pcie_replay_count,
.supports_baco = &vi_asic_supports_baco,
- .pre_asic_init = &vi_pre_asic_init,
.query_video_codecs = &vi_query_video_codecs,
};