With the spi-qpic-snand driver now supporting reading ECC requirements
from the NAND chip itself, there's no need to set those in the DTS
anymore avoiding issues with devices of the same revision using
different NAND types with varying ECC requirements.
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
Link: https://github.com/openwrt/openwrt/pull/18723
Signed-off-by: Robert Marko <robimarko@gmail.com>
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
};
};
-&qpic_nand {
- nand@0 {
- nand-ecc-strength = <4>;
- };
-};
-
/*
* ===============================================================
* _______________________ _______________________
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
-
- nand-ecc-strength = <8>;
- nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {
#size-cells = <1>;
nand-ecc-engine = <&qpic_nand>;
-
- /* strength=8 breaks NAND I/O, use 4 instead */
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
nand-bus-width = <8>;
partitions {