riscv: dts: sophgo: Move riscv cpu definition to a separate file

As sg2000 and sg2002 can boot from an arm a53 core, it is not
suitable to left the riscv cpu definition in the common peripheral
header.

Move the riscv related device into a separate header file, so the
arm subsystem can reuse the common peripheral header.

Signed-off-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Link: https://lore.kernel.org/r/20250430012654.235830-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
index fc9e6b56790fc78429c1a70b8bcc8c66e6c12329..91bf4563e1f9d219afd8da9fdc8a62e6efdcfb2e 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
@@ -4,6 +4,7 @@
  */
 
 #include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
+#include "cv180x-cpus.dtsi"
 #include "cv18xx.dtsi"
 
 / {

diff --git a/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi b/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi
new file mode 100644 (file)
index 0000000..93fd9e4
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv180x-cpus.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+/ {
+       cpus: cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+               timebase-frequency = <25000000>;
+
+               cpu0: cpu@0 {
+                       compatible = "thead,c906", "riscv";
+                       device_type = "cpu";
+                       reg = <0>;
+                       d-cache-block-size = <64>;
+                       d-cache-sets = <512>;
+                       d-cache-size = <65536>;
+                       i-cache-block-size = <64>;
+                       i-cache-sets = <128>;
+                       i-cache-size = <32768>;
+                       mmu-type = "riscv,sv39";
+                       riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
+
+                       cpu0_intc: interrupt-controller {
+                               compatible = "riscv,cpu-intc";
+                               interrupt-controller;
+                               #interrupt-cells = <1>;
+                       };
+               };
+       };
+};

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
index fcea4376fb79c33ad4216aeb0bc007b50e18f158..cc094b3f585f457e0bd26a79c27e76717e5d96b2 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
+#include "cv180x-cpus.dtsi"
 #include "cv18xx.dtsi"
 #include "cv181x.dtsi"
 

diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
index a1129533576a7325383cb7eeace254fc90a07b99..6668476178bbd74c68fff122414f72cc0288a0e4 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi
@@ -12,35 +12,6 @@
        #address-cells = <1>;
        #size-cells = <1>;
 
-       cpus: cpus {
-               #address-cells = <1>;
-               #size-cells = <0>;
-               timebase-frequency = <25000000>;
-
-               cpu0: cpu@0 {
-                       compatible = "thead,c906", "riscv";
-                       device_type = "cpu";
-                       reg = <0>;
-                       d-cache-block-size = <64>;
-                       d-cache-sets = <512>;
-                       d-cache-size = <65536>;
-                       i-cache-block-size = <64>;
-                       i-cache-sets = <128>;
-                       i-cache-size = <32768>;
-                       mmu-type = "riscv,sv39";
-                       riscv,isa = "rv64imafdc";
-                       riscv,isa-base = "rv64i";
-                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
-                                              "zifencei", "zihpm";
-
-                       cpu0_intc: interrupt-controller {
-                               compatible = "riscv,cpu-intc";
-                               interrupt-controller;
-                               #interrupt-cells = <1>;
-                       };
-               };
-       };
-
        osc: oscillator {
                compatible = "fixed-clock";
                clock-output-names = "osc_25m";

diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
index df133831bd3e2985b7a6e22aafd47e53f4925f88..6f02de9b098216529749c2af8ea2eae70a22115c 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi
@@ -5,6 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/pinctrl-sg2002.h>
+#include "cv180x-cpus.dtsi"
 #include "cv18xx.dtsi"
 #include "cv181x.dtsi"