re PR target/58838 (mullw sets condition code incorrectly.)

        PR target/58838
        * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add
        TARGET_32BIT final condition.
        (mulsi3_internal2 and splitter): Same.

From-SVN: r203977

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index acd6620a048c0a31c645425666590f954afec850..cf5fef27704417be011ce9d7c635f32a0a8d57b0 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2013-10-23  David Edelsohn  <dje.gcc@gmail.com>
+
+       PR target/58838
+       * config/rs6000/rs6000.md (mulsi3_internal1 and splitter): Add
+       TARGET_32BIT final condition.
+       (mulsi3_internal2 and splitter): Same.
+
 2013-10-23  Jeff Law  <law@redhat.com>
 
        * tree-ssa-threadedge.c (thread_across_edge): Do not allow threading

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 567961a42e54b6eedf236006f334cdbbc7d792c9..9a0472d21a9eb5b89d0dd45360e4cb823077b073 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2699,7 +2699,7 @@
                             (match_operand:SI 2 "gpc_reg_operand" "r,r"))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))]
-  ""
+  "TARGET_32BIT"
   "@
    mullw. %3,%1,%2
    #"
@@ -2712,7 +2712,7 @@
                             (match_operand:SI 2 "gpc_reg_operand" ""))
                    (const_int 0)))
    (clobber (match_scratch:SI 3 ""))]
-  "reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 3)
        (mult:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
@@ -2727,7 +2727,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
        (mult:SI (match_dup 1) (match_dup 2)))]
-  ""
+  "TARGET_32BIT"
   "@
    mullw. %0,%1,%2
    #"
@@ -2741,7 +2741,7 @@
                    (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "")
        (mult:SI (match_dup 1) (match_dup 2)))]
-  "reload_completed"
+  "TARGET_32BIT && reload_completed"
   [(set (match_dup 0)
        (mult:SI (match_dup 1) (match_dup 2)))
    (set (match_dup 3)