]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
drm/msm/dpu: drop vbif_idx from WB configuration
authorDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Fri, 27 Feb 2026 18:36:44 +0000 (20:36 +0200)
committerDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Wed, 25 Mar 2026 06:06:20 +0000 (08:06 +0200)
All MDP / DPU implementations except for MSM8996 use VBIF_RT (or the
only VBIF) for WB2. Writeback on MSM8996 is not supported (nor planned
to be supported). In order to simplify the driver, drop the field form
the struct dpu_wb_cfg.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/707778/
Link: https://lore.kernel.org/r/20260227-drop-vbif-nrt-v1-5-2b97d0438182@oss.qualcomm.com
[DB: also handled Eliza platform]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
22 files changed:
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_2_glymur.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_4_eliza.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_13_0_kaanapali.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h

index b31cb6f16f33e080792787bfefd46b1ca47bf490..db79f9382f8b4e2c3a09018923f9f2246b3ead1d 100644 (file)
@@ -322,7 +322,6 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index b0c38b2e38c4e20f3916d63bdd76c0ea23c46ad4..59caa2c2a87c4b9fe86523ff17181193a007e3c4 100644 (file)
@@ -364,7 +364,6 @@ static const struct dpu_wb_cfg sm8750_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index f6fd79a485376870b83a9f64dc7f0441d6014789..5e24309b46748e45e357b5ac5e6e0f33dc45cd47 100644 (file)
@@ -371,7 +371,6 @@ static const struct dpu_wb_cfg glymur_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index aeccf6f9095e3ee301cdd34ae1e37078b2119d10..b482a7e4e6c06aa3b9612b7a93fa361fec303ade 100644 (file)
@@ -235,7 +235,6 @@ static const struct dpu_wb_cfg eliza_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 02d2de6073f84963a4ad511f211b486981089250..bf1940d9c9e90b1956cb5c612c1082ec275b6106 100644 (file)
@@ -362,7 +362,6 @@ static const struct dpu_wb_cfg kaanapali_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 9f43ce8bf31b1b4dd8e8c07a11d3584961b020dd..e61e14572affb116cd2eb5db6a2e505e201f9be1 100644 (file)
@@ -280,7 +280,6 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 14611a34437166969cc784a23e1d881b3bf6fbf9..fb18de029e80df142dab8120778c218935701d96 100644 (file)
@@ -286,7 +286,6 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 7b97e3b8630ee7df0ece82b70e89389c121be06f..ffb89a03cfade79bf26c78211d460fd950046e93 100644 (file)
@@ -246,7 +246,6 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 65fbd006720d91e2fb793a4b0b82e6c4a689b25a..427ecd4cbf63d2213b39ff4a83f90a705faedd6c 100644 (file)
@@ -158,7 +158,6 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 2160,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index c7833ca05eb463bc2b5d3cc5f91eebaaa8ce8c6a..64be51e301591b7f17918475a957623c6fea23d4 100644 (file)
@@ -137,7 +137,6 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 2160,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 09ca22b93e68bc772b766f22b11dd54309aa5919..c481e964fca06b92a3174d17fcb5231f5ee4425b 100644 (file)
@@ -317,7 +317,6 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 3adc3350f05b456ddbe993b04c86d6022b5b98a1..d6f7ee24ca933356ac86aac4ba8e78b1b5cf58ae 100644 (file)
@@ -153,7 +153,6 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 7b58e438f597dec7eddef27d0a4274ae55aa196f..dd891703e35f8f3587def4401e5e3e0267836c8e 100644 (file)
@@ -147,7 +147,6 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 1920,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index a3fea0ade6888f9cedd0eac9c11c4eb97a18e375..9afdfdb3be6fb7c8d690b310b5390e4b608dd3f1 100644 (file)
@@ -290,7 +290,6 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index ce38e93c0d7e399f54796020651dc84e94eb5dee..99b8a890fddc7a492f37509b0e44af17c781b70f 100644 (file)
@@ -172,7 +172,6 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 0271add0f2b977c0788d150fe704d778fd3a074b..bdab0ebfe10284c9f85eadb20b30d8f9959b2e0a 100644 (file)
@@ -303,7 +303,6 @@ static const struct dpu_wb_cfg sm8450_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index c9dff42d8ea1ada11ac3037fc85d27ddbad14d84..f3d85d173c56b6f46f4ac26dbe13313318953608 100644 (file)
@@ -310,7 +310,6 @@ static const struct dpu_wb_cfg sa8775p_wb[] = {
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .clk_ctrl = DPU_CLK_CTRL_WB2,
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index c0c133ffd5554fea738dc1b8b7ee408897a40c47..5837e252f5d23401be3ded9fe9ebbae88ad9a8ee 100644 (file)
@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sm8550_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 4e1edf69b22550006707c2fa0b02f04c3ce74e73..9cc0b7ea3a307d19e069b349d9f2d6f9a5dd7687 100644 (file)
@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg sar2130p_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index fce95fadefcaff3ea4df8e9899afb9b12c80c3b8..10443368f682925f628e294c7d2cf32899e7240b 100644 (file)
@@ -298,7 +298,6 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
                .format_list = wb2_formats_rgb_yuv,
                .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
                .xin_id = 6,
-               .vbif_idx = VBIF_RT,
                .maxlinewidth = 4096,
                .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
        },
index 6d28f2281c7657454ed804116e160d94c8d07192..73021aaa8d3ff9bc75c918328b45d28d066ec2c4 100644 (file)
@@ -70,7 +70,8 @@ static void dpu_encoder_phys_wb_set_ot_limit(
        ot_params.height = phys_enc->cached_mode.vdisplay;
        ot_params.is_wfd = !dpu_encoder_helper_get_cwb_mask(phys_enc);
        ot_params.frame_rate = drm_mode_vrefresh(&phys_enc->cached_mode);
-       ot_params.vbif_idx = hw_wb->caps->vbif_idx;
+       /* XXX: WB on MSM8996 should use VBIF_NRT */
+       ot_params.vbif_idx = VBIF_RT;
        ot_params.rd = false;
 
        if (!_dpu_encoder_phys_wb_clk_force_ctrl(hw_wb, phys_enc->dpu_kms->hw_mdp,
@@ -108,7 +109,8 @@ static void dpu_encoder_phys_wb_set_qos_remap(
        hw_wb = phys_enc->hw_wb;
 
        memset(&qos_params, 0, sizeof(qos_params));
-       qos_params.vbif_idx = hw_wb->caps->vbif_idx;
+       /* XXX: WB on MSM8996 should use VBIF_NRT */
+       qos_params.vbif_idx = VBIF_RT;
        qos_params.xin_id = hw_wb->caps->xin_id;
        qos_params.num = hw_wb->idx - WB_0;
        qos_params.is_rt = dpu_encoder_helper_get_cwb_mask(phys_enc);
index c43ee4016db4712f544d1ed56ebd98600327055f..ba04ac24d5a9e4167337acd9299e1012f6f8eb5f 100644 (file)
@@ -524,7 +524,6 @@ struct dpu_intf_cfg  {
 /**
  * struct dpu_wb_cfg - information of writeback blocks
  * @DPU_HW_BLK_INFO:    refer to the description above for DPU_HW_BLK_INFO
- * @vbif_idx:           vbif client index
  * @maxlinewidth:       max line width supported by writeback block
  * @xin_id:             bus client identifier
  * @intr_wb_done:       interrupt index for WB_DONE
@@ -535,7 +534,6 @@ struct dpu_intf_cfg  {
 struct dpu_wb_cfg {
        DPU_HW_BLK_INFO;
        unsigned long features;
-       u8 vbif_idx;
        u32 maxlinewidth;
        u32 xin_id;
        unsigned int intr_wb_done;