drm/amd/display: Move setup_stream_attribute

[ Upstream commit 2681bf4ae8d24df950138b8c9ea9c271cd62e414 ]

[WHY]
If symclk RCO is enabled, stream encoder may not be receiving an ungated
clock by the time we attempt to set stream attributes when setting dpms
on. Since the clock is gated, register writes to the stream encoder fail.

[HOW]
Move set_stream_attribute call into enable_stream, just after the point
where symclk32_se is ungated.
Logically there is no need to set stream attributes as early as is
currently done in link_set_dpms_on, so this should have no impact beyond
the RCO fix.

Reviewed-by: Ovidiu (Ovi) Bunea <ovidiu.bunea@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Ivan Lipski <ivan.lipski@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 03b22e9115ea8ad1664e5122fcd079a0574c4350..9e5cb609e89eebdf22bdf085ff9e94285bafd4e4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -670,6 +670,7 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
        uint32_t early_control = 0;
        struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
+       link_hwss->setup_stream_attribute(pipe_ctx);
        link_hwss->setup_stream_encoder(pipe_ctx);
 
        dc->hwss.update_info_frame(pipe_ctx);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index d96f52a551940d7cfe11aefb7272f69e31b9c48d..55f067c9e4948b20ed1c72f6c25b9e477c95a6df 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3009,6 +3009,8 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
                                                      link_enc->transmitter - TRANSMITTER_UNIPHY_A);
        }
 
+       link_hwss->setup_stream_attribute(pipe_ctx);
+
        if (dc->res_pool->dccg->funcs->set_pixel_rate_div)
                dc->res_pool->dccg->funcs->set_pixel_rate_div(
                        dc->res_pool->dccg,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index bcb296a954f2b48f52e62bcce5e2408ab15e21d6..f1a3e7089380518a53ed07df8d8d143782275041 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1019,6 +1019,8 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
                }
        }
 
+       link_hwss->setup_stream_attribute(pipe_ctx);
+
        if (dc->res_pool->dccg->funcs->set_pixel_rate_div) {
                dc->res_pool->dccg->funcs->set_pixel_rate_div(
                        dc->res_pool->dccg,

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 9d740659521a4370230ebd50a8d2c25a084b7012..f6ab52979e331ca62770b9041c7137dae852b47e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2447,7 +2447,6 @@ void link_set_dpms_on(
        struct link_encoder *link_enc;
        enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
        struct vpg *vpg = pipe_ctx->stream_res.stream_enc->vpg;
-       const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res);
        bool apply_edp_fast_boot_optimization =
                pipe_ctx->stream->apply_edp_fast_boot_optimization;
 
@@ -2490,8 +2489,6 @@ void link_set_dpms_on(
                pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
        }
 
-       link_hwss->setup_stream_attribute(pipe_ctx);
-
        pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
 
        // Enable VPG before building infoframe

diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
index ad088d70e1893220675b91f0234a8d3a66a7adf1..6ffc74fc9dcd86be73615ccd85c6b740f7243955 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c
@@ -44,6 +44,11 @@ static void virtual_stream_encoder_dvi_set_stream_attribute(
        struct dc_crtc_timing *crtc_timing,
        bool is_dual_link) {}
 
+static void virtual_stream_encoder_lvds_set_stream_attribute(
+       struct stream_encoder *enc,
+       struct dc_crtc_timing *crtc_timing)
+{}
+
 static void virtual_stream_encoder_set_throttled_vcp_size(
        struct stream_encoder *enc,
        struct fixed31_32 avg_time_slots_per_mtp)
@@ -115,6 +120,8 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = {
                virtual_stream_encoder_hdmi_set_stream_attribute,
        .dvi_set_stream_attribute =
                virtual_stream_encoder_dvi_set_stream_attribute,
+       .lvds_set_stream_attribute =
+               virtual_stream_encoder_lvds_set_stream_attribute,
        .set_throttled_vcp_size =
                virtual_stream_encoder_set_throttled_vcp_size,
        .update_hdmi_info_packets =