return link_speed[speed_level];
}
-static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
- enum pp_clock_type type, char *buf)
+static int vega12_emit_clock_levels(struct pp_hwmgr *hwmgr,
+ enum pp_clock_type type, char *buf,
+ int *offset)
{
- int i, now, size = 0;
struct pp_clock_levels_with_latency clocks;
+ int i, now, size = *offset;
switch (type) {
case PP_SCLK:
"Attempt to get gfx clk levels Failed!",
return -1);
for (i = 0; i < clocks.num_levels; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
+ size += sysfs_emit_at(
+ buf, size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz / 1000 ==
+ now / 100) ?
+ "*" :
+ "");
break;
case PP_MCLK:
"Attempt to get memory clk levels Failed!",
return -1);
for (i = 0; i < clocks.num_levels; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
+ size += sysfs_emit_at(
+ buf, size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz / 1000 ==
+ now / 100) ?
+ "*" :
+ "");
break;
case PP_SOCCLK:
"Attempt to get soc clk levels Failed!",
return -1);
for (i = 0; i < clocks.num_levels; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+ size += sysfs_emit_at(
+ buf, size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz / 1000 == now) ?
+ "*" :
+ "");
break;
case PP_DCEFCLK:
"Attempt to get dcef clk levels Failed!",
return -1);
for (i = 0; i < clocks.num_levels; i++)
- size += sprintf(buf + size, "%d: %uMhz %s\n",
- i, clocks.data[i].clocks_in_khz / 1000,
- (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
+ size += sysfs_emit_at(
+ buf, size, "%d: %uMhz %s\n", i,
+ clocks.data[i].clocks_in_khz / 1000,
+ (clocks.data[i].clocks_in_khz / 1000 == now) ?
+ "*" :
+ "");
break;
case PP_PCIE:
default:
break;
}
- return size;
+
+ *offset = size;
+
+ return 0;
}
static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
.set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
.display_clock_voltage_request = vega12_display_clock_voltage_request,
.force_clock_level = vega12_force_clock_level,
- .print_clock_levels = vega12_print_clock_levels,
+ .emit_clock_levels = vega12_emit_clock_levels,
.apply_clocks_adjust_rules =
vega12_apply_clocks_adjust_rules,
.pre_display_config_changed =