drm/msm/adreno: Add Adreno X1-45 support

Add support for Adreno X1-45 GPU present Snapdragon X1P42100
series of compute chipsets. This GPU is a smaller version of
X1-85 GPU with lower core count and smaller internal memories.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/660217/
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 301181138b60a3edb7f28c72d2908b3cf7f6a183..2fdaaf4372d381c351df92b8dcb21da0fcd02776 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1481,6 +1481,45 @@ static const struct adreno_info a7xx_gpus[] = {
                        },
                },
                .preempt_record_size = 3572 * SZ_1K,
+       }, {
+               .chip_ids = ADRENO_CHIP_IDS(0x43030c00),
+               .family = ADRENO_7XX_GEN2,
+               .fw = {
+                       [ADRENO_FW_SQE] = "gen71500_sqe.fw",
+                       [ADRENO_FW_GMU] = "gen71500_gmu.bin",
+               },
+               .gmem = SZ_1M + SZ_512K,
+               .inactive_period = DRM_MSM_INACTIVE_PERIOD,
+               .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+                         ADRENO_QUIRK_HAS_HW_APRIV |
+                         ADRENO_QUIRK_PREEMPTION,
+               .init = a6xx_gpu_init,
+               .a6xx = &(const struct a6xx_info) {
+                       .hwcg = a740_hwcg,
+                       .protect = &a730_protect,
+                       .pwrup_reglist = &a7xx_pwrup_reglist,
+                       .gmu_chipid = 0x70f0000,
+                       .gmu_cgc_mode = 0x00020222,
+                       .bcms = (const struct a6xx_bcm[]) {
+                               { .name = "SH0", .buswidth = 16 },
+                               { .name = "MC0", .buswidth = 4 },
+                               {
+                                       .name = "ACV",
+                                       .fixed = true,
+                                       .perfmode = BIT(3),
+                                       .perfmode_bw = 16500000,
+                               },
+                               { /* sentinel */ },
+                       },
+               },
+               .preempt_record_size = 4192 * SZ_1K,
+               .speedbins = ADRENO_SPEEDBINS(
+                       { 0,   0 },
+                       { 294, 1 },
+                       { 263, 2 },
+                       { 233, 3 },
+                       { 141, 4 },
+               ),
        }
 };
 DECLARE_ADRENO_GPULIST(a7xx);