arm64: dts: exynos: gs101: add cmu_dpu and sysreg_dpu dt nodes

Enable the cmu_dpu clock management unit. It feeds some of the display
IPs. Additionally add the sysreg_dpu node which contains the
BUSCOMPONENT_DRCG_EN and MEMCLK registers required by cmu_dpu to enable
dynamic root clock gating of bus components.

Reviewed-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-5-cb85424f2c72@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index 48f3819590cf8c05d6bd7241cfed8720149c7db4..d085f9fb0f62ac2f57b104c20880e64d885d0bee 100644 (file)
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -1815,6 +1815,23 @@
                        status = "disabled";
                };
 
+               cmu_dpu: clock-controller@1c000000 {
+                       compatible = "google,gs101-cmu-dpu";
+                       reg = <0x1c000000 0x10000>;
+                       #clock-cells = <1>;
+
+                       clocks = <&ext_24_5m>,
+                                <&cmu_top CLK_DOUT_CMU_DPU_BUS>;
+                       clock-names = "oscclk", "bus";
+                       samsung,sysreg = <&sysreg_dpu>;
+               };
+
+               sysreg_dpu: syscon@1c020000 {
+                       compatible = "google,gs101-dpu-sysreg", "syscon";
+                       reg = <0x1c020000 0x10000>;
+                       clocks = <&cmu_dpu CLK_GOUT_DPU_SYSREG_DPU_PCLK>;
+               };
+
                cmu_top: clock-controller@1e080000 {
                        compatible = "google,gs101-cmu-top";
                        reg = <0x1e080000 0x10000>;