arm64: dts: exynos: gs101: add CPU clocks

Add the GS101 CPU clocks exposed through the ACPM protocol.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Tested-by: Peter Griffin <peter.griffin@linaro.org> # on gs101-oriole
Link: https://patch.msgid.link/20250924-acpm-dvfs-dt-v4-2-3106d49e03f5@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
index f88d45a368af7ef88e8cdc84b3a81a63a753832c..7326801c9ebf270496997839185594c3c1776577 100644 (file)
--- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
+++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
@@ -7,6 +7,7 @@
  */
 
 #include <dt-bindings/clock/google,gs101.h>
+#include <dt-bindings/clock/google,gs101-acpm.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/samsung,exynos-usi.h>
@@ -72,6 +73,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0000>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
                        enable-method = "psci";
                        cpu-idle-states = <&ananke_cpu_sleep>;
                        capacity-dmips-mhz = <250>;
@@ -82,6 +84,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0100>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
                        enable-method = "psci";
                        cpu-idle-states = <&ananke_cpu_sleep>;
                        capacity-dmips-mhz = <250>;
@@ -92,6 +95,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0200>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
                        enable-method = "psci";
                        cpu-idle-states = <&ananke_cpu_sleep>;
                        capacity-dmips-mhz = <250>;
@@ -102,6 +106,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a55";
                        reg = <0x0300>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL0>;
                        enable-method = "psci";
                        cpu-idle-states = <&ananke_cpu_sleep>;
                        capacity-dmips-mhz = <250>;
@@ -112,6 +117,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a76";
                        reg = <0x0400>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
                        enable-method = "psci";
                        cpu-idle-states = <&enyo_cpu_sleep>;
                        capacity-dmips-mhz = <620>;
@@ -122,6 +128,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a76";
                        reg = <0x0500>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL1>;
                        enable-method = "psci";
                        cpu-idle-states = <&enyo_cpu_sleep>;
                        capacity-dmips-mhz = <620>;
@@ -132,6 +139,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-x1";
                        reg = <0x0600>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
                        enable-method = "psci";
                        cpu-idle-states = <&hera_cpu_sleep>;
                        capacity-dmips-mhz = <1024>;
@@ -142,6 +150,7 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-x1";
                        reg = <0x0700>;
+                       clocks = <&acpm_ipc GS101_CLK_ACPM_DVFS_CPUCL2>;
                        enable-method = "psci";
                        cpu-idle-states = <&hera_cpu_sleep>;
                        capacity-dmips-mhz = <1024>;