mediatek: fix PHY autodetection on Cudy WR3000H

Newer Cudy WR3000H units have a Motorcomm YT8821 PHY instead of a
Realtek PHY on the WAN port. Before this commit, the Motorcomm PHY
could not be autodetected by the kernel -- the PHY would show up as
just a generic clause 45 PHY and the proper driver would not be loaded.

The cause of the detection failure likely was that the YT8821 PHY was
held in reset during PHY detection. To fix this, move the reset GPIO
definition to the MDIO bus level. This reset line is deasserted before
the autodetection process, see also [1]. With this change, both Realtek
and Motorcomm PHYs can be supported with a single device tree.

[1]: https://lore.kernel.org/all/20251119134750.394655-1-horatiu.vultur@microchip.com/

Signed-off-by: Jakub Vaněk <linuxtardis@gmail.com>
Link: https://github.com/openwrt/openwrt/pull/21399
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>

diff --git a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
index 69e1098b4341cf70c819df8fcbe7e3b5f6611feb..530748a4c69b35f0d307ddf25fbaab42c08f7a0c 100644 (file)
--- a/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
+++ b/target/linux/mediatek/dts/mt7981b-cudy-wr3000h-v1.dts
@@ -101,13 +101,17 @@
 };
 
 &mdio_bus {
+       /* We need to have the reset GPIO on the MDIO bus node,
+        * otherwise the PHY would be held in reset during PHY detection */
+       reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
+       reset-delay-us = <100000>;
+       reset-post-delay-us = <100000>;
 
        phy6: ethernet-phy@6 {
+               /* Either Realtek RTL8221B-VB-CG or Motorcomm YT8821,
+                * depending on HW revision */
                compatible = "ethernet-phy-ieee802.3-c45";
                reg = <6>;
-               reset-assert-us = <100000>;
-               reset-deassert-us = <100000>;
-               reset-gpios = <&pio 3 GPIO_ACTIVE_LOW>;
        };
 };