iommu/vt-d: Treat PAGE_SNOOP and PWSNP separately

The PASID_FLAG_PAGE_SNOOP and PASID_FLAG_PWSNP constants are identical.
This will cause the pasid code to always set both or neither of the
PGSNP and PWSNP bits in PASID table entries. However, PWSNP is a
reserved bit if SMPWC is not set in the IOMMU's extended capability
register, even if SC is supported.

This has resulted in DMAR errors when testing the iommufd code on an
Arrow Lake platform. With this patch, those errors disappear and the
PASID table entries look correct.

Fixes: 101a2854110fa ("iommu/vt-d: Follow PT_FEAT_DMA_INCOHERENT into the PASID entry")
Cc: stable@vger.kernel.org
Signed-off-by: Viktor Kleen <viktor@kleen.org>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Link: https://lore.kernel.org/r/20260202192109.1665799-1-viktor@kleen.org
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

diff --git a/drivers/iommu/intel/pasid.h b/drivers/iommu/intel/pasid.h
index b4c85242dc7962543c777df2da9d43bfa506a117..3809793e0259f11cf8c9914d4964ff6f5dbb8e47 100644 (file)
--- a/drivers/iommu/intel/pasid.h
+++ b/drivers/iommu/intel/pasid.h
@@ -24,7 +24,7 @@
 
 #define PASID_FLAG_NESTED              BIT(1)
 #define PASID_FLAG_PAGE_SNOOP          BIT(2)
-#define PASID_FLAG_PWSNP               BIT(2)
+#define PASID_FLAG_PWSNP               BIT(3)
 
 /*
  * The PASID_FLAG_FL5LP flag Indicates using 5-level paging for first-