RISC-V: Add vector_scalar_shift_operand

The vector shift immediates happen to have the same constraints as some
of the CSR-related operands, but it's a different usage.  This adds a
name for them, so I don't get confused again next time.

gcc/ChangeLog:

	* config/riscv/autovec.md (shifts): Use
	vector_scalar_shift_operand.
	* config/riscv/predicates.md (vector_scalar_shift_operand): New
	predicate.

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 3e0a1da365199da9a143a0d1a43cfaa11697bb2e..4f6fbf57d301d96ace13cef67e7fc1b628c3f22a 100644 (file)
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -440,10 +440,10 @@
 ;; -------------------------------------------------------------------------
 
 (define_insn_and_split "<optab><mode>3"
-  [(set (match_operand:V_VLSI 0 "register_operand" "=vr")
+  [(set (match_operand:V_VLSI 0 "register_operand"        "=vr")
     (any_shift:V_VLSI
-     (match_operand:V_VLSI 1 "register_operand"    " vr")
-     (match_operand:<VEL> 2 "csr_operand"      " rK")))]
+     (match_operand:V_VLSI 1 "register_operand"           " vr")
+     (match_operand:<VEL> 2 "vector_scalar_shift_operand" " rK")))]
   "TARGET_VECTOR && can_create_pseudo_p ()"
   "#"
   "&& 1"

diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 3be87dfe96f8aa9b9423719d7b609336dc99fd00..53e7c1d03aa684f410d4c823fe6ff44bfcd5477c 100644 (file)
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -49,6 +49,11 @@
   (ior (match_operand 0 "const_csr_operand")
        (match_operand 0 "register_operand")))
 
+;; V has 32-bit unsigned immediates.  This happens to be the same constraint as
+;; the csr_operand, but it's not CSR related.
+(define_predicate "vector_scalar_shift_operand"
+  (match_operand 0 "csr_operand"))
+
 (define_predicate "sle_operand"
   (and (match_code "const_int")
        (match_test "SMALL_OPERAND (INTVAL (op) + 1)")))