]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
arm64: dts: renesas: r9a09g056: Add OSTM0-OSTM7 nodes
authorLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Wed, 14 May 2025 10:15:21 +0000 (11:15 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 10 Jun 2025 07:58:34 +0000 (09:58 +0200)
Add OSTM0-OSTM7 nodes to RZ/V2N ("R9A09G056") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250514101528.41663-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a09g056.dtsi

index 8aee35bba3fff297fe2f71d12382e66da8edb733..8b7b25a4f1d475254b230af4fb35718c02755a54 100644 (file)
                        resets = <&cpg 0x30>;
                };
 
+               ostm0: timer@11800000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x11800000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x43>;
+                       resets = <&cpg 0x6d>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm1: timer@11801000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x11801000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x44>;
+                       resets = <&cpg 0x6e>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm2: timer@14000000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x14000000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x45>;
+                       resets = <&cpg 0x6f>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm3: timer@14001000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x14001000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x46>;
+                       resets = <&cpg 0x70>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm4: timer@12c00000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x12c00000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x47>;
+                       resets = <&cpg 0x71>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm5: timer@12c01000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x12c01000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x48>;
+                       resets = <&cpg 0x72>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm6: timer@12c02000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x12c02000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x49>;
+                       resets = <&cpg 0x73>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               ostm7: timer@12c03000 {
+                       compatible = "renesas,r9a09g056-ostm", "renesas,ostm";
+                       reg = <0x0 0x12c03000 0x0 0x1000>;
+                       interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&cpg CPG_MOD 0x4a>;
+                       resets = <&cpg 0x74>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                scif: serial@11c01400 {
                        compatible = "renesas,scif-r9a09g056",
                                     "renesas,scif-r9a09g057";