drm/amd/display: prevent hang on link training fail

commit 8058061ed9d6bc259d1e678607b07d259342c08f upstream.

[Why]
When link training fails, the phy clock will be disabled. However, in
enable_streams, it is assumed that link training succeeded and the
mux selects the phy clock, causing a hang when a register write is made.

[How]
When enable_stream is hit, check if link training failed. If it did, fall
back to the ref clock to avoid a hang and keep the system in a recoverable
state.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Brendan Tam <Brendan.Tam@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 36d12db8d022566307288c5dbee7804f7029b7c3..f5f1ccd8303cf37fee51139bd5c41d0075a01092 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -3003,7 +3003,11 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
                dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);
 
                phyd32clk = get_phyd32clk_src(link);
-               dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
+               if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {
+                       dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
+               } else {
+                       dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
+               }
        } else {
                if (dccg->funcs->enable_symclk_se)
                        dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 0b743669f23b44949bd41cedf9b035e36b46fb85..62f1e597787e69a76cc7564f0ec2e49b2fa385a2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1001,8 +1001,11 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx)
        if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) {
                if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {
                        dccg->funcs->set_dpstreamclk(dccg, DPREFCLK, tg->inst, dp_hpo_inst);
-
-                       dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
+                       if (link->cur_link_settings.link_rate == LINK_RATE_UNKNOWN) {
+                               dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);
+                       } else {
+                               dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);
+                       }
                } else {
                        /* need to set DTBCLK_P source to DPREFCLK for DP8B10B */
                        dccg->funcs->set_dtbclk_p_src(dccg, DPREFCLK, tg->inst);