lspci: Decode Physical Layer 64 GT/s extended capability register

diff --git a/lib/header.h b/lib/header.h
index 3dc43b3d7b9e6fe67f2479b5abe68aefecb4c8ef..7c76849898526cc3214f3842a2f906db5477fedb 100644 (file)
--- a/lib/header.h
+++ b/lib/header.h
@@ -257,6 +257,7 @@
 #define PCI_EXT_CAP_ID_32GT    0x2a    /* Physical Layer 32.0 GT/s */
 #define PCI_EXT_CAP_ID_DOE     0x2e    /* Data Object Exchange */
 #define PCI_EXT_CAP_ID_IDE     0x30    /* Integrity and Data Encryption */
+#define PCI_EXT_CAP_ID_64GT    0x31    /* Physical Layer 64.0 GT/s */
 
 /*** Definitions of capabilities ***/
 
@@ -1407,6 +1408,19 @@
 #define PCI_32GT_TXMODTS1      0x18    /* Transmitted Modified TS Data 1 Register */
 #define PCI_32GT_TXMODTS2      0x1C    /* Transmitted Modified TS Data 2 Register */
 
+/* Physical Layer 64 GT/s Extended Capability */
+#define PCI_64GT_CAP           0x04    /* 64 GT/s Capabilities Register */
+#define PCI_64GT_CTL           0x08    /* 64 GT/s Control Register */
+#define PCI_64GT_STATUS                0x0C    /* 64 GT/s Status Register */
+#define  PCI_64GT_STATUS_EQU_COMP      0x0001  /* Equalization 64 GT/s Complete */
+#define  PCI_64GT_STATUS_EQU_PHASE1    0x0002  /* Equalization 64 GT/s Phase 1 Successful */
+#define  PCI_64GT_STATUS_EQU_PHASE2    0x0004  /* Equalization 64 GT/s Phase 2 Successful */
+#define  PCI_64GT_STATUS_EQU_PHASE3    0x0008  /* Equalization 64 GT/s Phase 3 Successful */
+#define  PCI_64GT_STATUS_EQU_REQ       0x0010  /* Link Equalization Request 64 GT/s */
+#define  PCI_64GT_STATUS_TX_PRE_ON     0x0020  /* Transmitter Precoding On */
+#define  PCI_64GT_STATUS_TX_PRE_REQ    0x0040  /* Transmitter Precoding Request */
+#define  PCI_64GT_STATUS_NO_EQU        0x0080  /* No Equalization Needed Received */
+
 /* Process Address Space ID */
 #define PCI_PASID_CAP          0x04    /* PASID feature register */
 #define  PCI_PASID_CAP_EXEC    0x02    /* Exec permissions Supported */

diff --git a/ls-ecaps.c b/ls-ecaps.c
index a725aedff0319c4f079f7c523996458386b48e28..0a7d906e4e3bae794a67ee3de3cf57ad68b4441a 100644 (file)
--- a/ls-ecaps.c
+++ b/ls-ecaps.c
@@ -815,6 +815,33 @@ cap_phy_32gt(struct device *d, int where)
          FLAG(status, PCI_32GT_STATUS_NO_EQU));
 }
 
+static void
+cap_phy_64gt(struct device *d, int where)
+{
+  printf("Physical Layer 64.0 GT/s\n");
+
+  if (verbose < 2)
+    return;
+
+  if (!config_fetch(d, where + PCI_64GT_CAP, 0x0C)) {
+    printf("\t\t<unreadable>\n");
+    return;
+  }
+
+  u32 status = get_conf_long(d, where + PCI_64GT_STATUS);
+
+  printf("\t\tPhy64Sta: EquComplete%c EquPhase1%c EquPhase2%c EquPhase3%c LinkEquRequest%c\n"
+         "\t\t\t  TxPrecodeOn%c TxPrecodeReq%c NoEqualizationNeededRecv%c\n",
+         FLAG(status, PCI_64GT_STATUS_EQU_COMP),
+         FLAG(status, PCI_64GT_STATUS_EQU_PHASE1),
+         FLAG(status, PCI_64GT_STATUS_EQU_PHASE2),
+         FLAG(status, PCI_64GT_STATUS_EQU_PHASE3),
+         FLAG(status, PCI_64GT_STATUS_EQU_REQ),
+         FLAG(status, PCI_64GT_STATUS_TX_PRE_ON),
+         FLAG(status, PCI_64GT_STATUS_TX_PRE_REQ),
+         FLAG(status, PCI_64GT_STATUS_NO_EQU));
+}
+
 static void
 cxl_range(u64 base, u64 size, int n)
 {
@@ -1942,6 +1969,9 @@ show_ext_caps(struct device *d, int type)
          case PCI_EXT_CAP_ID_IDE:
            cap_ide(d, where);
            break;
+         case PCI_EXT_CAP_ID_64GT:
+           cap_phy_64gt(d, where);
+           break;
          default:
            printf("Extended Capability ID %#02x\n", id);
            break;

diff --git a/setpci.c b/setpci.c
index e359ffdf9fadd3fd0c8cbb78f9ed0f946ead416b..4932b8de7dfcfcbb993dfe80b96fbb4a364bdf01 100644 (file)
--- a/setpci.c
+++ b/setpci.c
@@ -398,6 +398,7 @@ static const struct reg_name pci_reg_names[] = {
   { 0x20029,   0, 0, 0x0, "ECAP_NPEM" },
   { 0x2002a,   0, 0, 0x0, "ECAP_32GT" },
   { 0x20030,   0, 0, 0x0, "ECAP_IDE" },
+  { 0x20031,   0, 0, 0x0, "ECAP_64GT" },
   {       0,    0, 0, 0x0, NULL }
 };