+2015-06-17 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline:
+ 2015-07-10 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/sse.md (movdi_to_sse): Use gen_lowpart
+ and gen_higpart instead of gen_rtx_SUBREG.
+ * config/i386/i386.md
+ (floatdi<X87MODEF:mode>2_i387_with_xmm splitter): Ditto.
+ (read-modify peephole2): Use gen_lowpart instead of
+ gen_rtx_SUBREG for operand 5.
+
+2015-06-17 Uros Bizjak <ubizjak@gmail.com>
+
+ Backport from mainline:
+ 2015-07-08 Uros Bizjak <ubizjak@gmail.com>
+
+ PR target/66814
+ * config/i386/predicates.md (nonimmediate_gr_operand): New predicate.
+ * config/i386/i386.md (not peephole2): Use nonimmediate_gr_operand.
+ (varous peephole2s): Use {GENERAL,SSE,MMX}_REGNO_P instead of
+ {GENERAL,SSE,MMX}_REG_P where appropriate.
+
2015-07-10 Mantas Mikaitis <Mantas.Mikaitis@arm.com>
* config/arm/arm.h (TARGET_NEON_FP): Remove conditional definition,
2015-07-09 Iain Sandoe <iain@codesourcery.com>
PR target/66523
- * config/darwin.c (darwin_mark_decl_preserved): Exclude 'L' label names from
- preservation.
+ * config/darwin.c (darwin_mark_decl_preserved): Exclude 'L' label
+ names from preservation.
2015-07-07 Kaz Kojima <kkojima@gcc.gnu.org>
/* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
Assemble the 64-bit DImode value in an xmm register. */
emit_insn (gen_sse2_loadld (operands[3], CONST0_RTX (V4SImode),
- gen_rtx_SUBREG (SImode, operands[1], 0)));
+ gen_lowpart (SImode, operands[1])));
emit_insn (gen_sse2_loadld (operands[4], CONST0_RTX (V4SImode),
- gen_rtx_SUBREG (SImode, operands[1], 4)));
+ gen_highpart (SImode, operands[1])));
emit_insn (gen_vec_interleave_lowv4si (operands[3], operands[3],
- operands[4]));
+ operands[4]));
operands[3] = gen_rtx_REG (DImode, REGNO (operands[3]));
})
;; lifetime information then.
(define_peephole2
- [(set (match_operand:SWI124 0 "nonimmediate_operand")
- (not:SWI124 (match_operand:SWI124 1 "nonimmediate_operand")))]
+ [(set (match_operand:SWI124 0 "nonimmediate_gr_operand")
+ (not:SWI124 (match_operand:SWI124 1 "nonimmediate_gr_operand")))]
"optimize_insn_for_speed_p ()
&& ((TARGET_NOT_UNPAIRABLE
&& (!MEM_P (operands[0])
[(match_dup 0)
(match_operand 2 "memory_operand")]))]
"REGNO (operands[0]) != REGNO (operands[1])
- && ((MMX_REG_P (operands[0]) && MMX_REG_P (operands[1]))
- || (SSE_REG_P (operands[0]) && SSE_REG_P (operands[1])))"
+ && ((MMX_REGNO_P (REGNO (operands[0]))
+ && MMX_REGNO_P (REGNO (operands[1])))
+ || (SSE_REGNO_P (REGNO (operands[0]))
+ && SSE_REGNO_P (REGNO (operands[1]))))"
[(set (match_dup 0) (match_dup 2))
(set (match_dup 0)
(match_op_dup 3 [(match_dup 0) (match_dup 1)]))])
(match_operand 1 "const0_operand"))]
"GET_MODE_SIZE (GET_MODE (operands[0])) <= UNITS_PER_WORD
&& (! TARGET_USE_MOV0 || optimize_insn_for_size_p ())
- && GENERAL_REG_P (operands[0])
+ && GENERAL_REGNO_P (REGNO (operands[0]))
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int 0))
(clobber (reg:CC FLAGS_REG))])]
[(set (match_operand:SWI248 0 "register_operand")
(const_int -1))]
"(optimize_insn_for_size_p () || TARGET_MOVE_M1_VIA_OR)
+ && GENERAL_REGNO_P (REGNO (operands[0]))
&& peep2_regno_dead_p (0, FLAGS_REG)"
[(parallel [(set (match_dup 0) (const_int -1))
(clobber (reg:CC FLAGS_REG))])]
operands[1] = gen_rtx_PLUS (word_mode, base,
gen_rtx_MULT (word_mode, index, GEN_INT (scale)));
- operands[5] = base;
if (mode != word_mode)
operands[1] = gen_rtx_SUBREG (mode, operands[1], 0);
+
+ operands[5] = base;
if (op1mode != word_mode)
- operands[5] = gen_rtx_SUBREG (op1mode, operands[5], 0);
+ operands[5] = gen_lowpart (op1mode, operands[5]);
+
operands[0] = dest;
})
\f
/* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
Assemble the 64-bit DImode value in an xmm register. */
emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode),
- gen_rtx_SUBREG (SImode, operands[1], 0)));
+ gen_lowpart (SImode, operands[1])));
emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode),
- gen_rtx_SUBREG (SImode, operands[1], 4)));
+ gen_highpart (SImode, operands[1])));
emit_insn (gen_vec_interleave_lowv4si (operands[0], operands[0],
operands[2]));
}